M14D1G1664A-2D Datasheet, PDF (30/64 Pages) Elite Semiconductor Memory Technology Inc. – Internal pipelined double-data-rate architecture; two data access per clock cycle

ESMT
Extended Mode Register Set-3 [EMRS(3)]
M14D1G1664A (2D)
BA2 BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0
1
1
0
BA2 BA1 BA0
Mode Register
0 0 0 MRS
0 0 1 EMRS(1)
0 1 0 EMRS(2)
0 1 1 EMRS(3): Reserved
Note: EMRS(3) is reserved for future. All bits except BA0 ~ BA2 are reserved for future use and must be set to 0 when
setting to mode register during initialization.
Elite Semiconductor Memory Technology Inc.
Publication Date : Aug. 2013
Revision : 1.3
30/64