M14D1G1664A-2D Datasheet, PDF (20/64 Pages) Elite Semiconductor Memory Technology Inc. – Internal pipelined double-data-rate architecture; two data access per clock cycle

ESMT
M14D1G1664A (2D)
Input Slew Rate De-rating
For all input signals the total t_IS, t_DS (setup time) and t_IH, t_DH (hold time) required is calculated by adding the data sheet t_IS (base), t_DS
(base) and t_IH (base), t_DH (base) value to the Δt_IS, Δt_DS and Δt_IH, Δt_DH de-rating value respectively.
Example: t_DS (total setup time) = t_DS (base) + Δt_DS.
Setup (t_IS, t_DS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of V_REF (DC) and the first
crossing of V_IH (AC)(min.). Setup (t_IS, t_DS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing
of V_REF (DC) and the first crossing of V_IL (AC)(max.). If the actual signal is always earlier than the nominal slew rate line between
shaded ‘V_REF (DC) to AC region’, use nominal slew rate for de-rating value (See the figure of Slew Rate Definition Nominal).
If the actual signal is later than the nominal slew rate line anywhere between shaded ‘V_REF (DC) to AC region’, the slew rate of a
tangent line to the actual signal from the AC level to DC level is used for de-rating value (see the figure of Slew Rate Definition
Tangent).
Hold (t_IH, t_DH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of V_IL (DC)(max.) and the
first crossing of V_REF (DC). Hold (t_IH, t_DH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing
of V_IH (DC)(min.) and the first crossing of V_REF (DC). If the actual signal is always later than the nominal slew rate line between
shaded ‘DC level to V_REF (DC) region’, use nominal slew rate for de-rating value (See the figure of Slew Rate Definition Nominal).
If the actual signal is earlier than the nominal slew rate line anywhere between shaded ‘DC to V_REF (DC) region’, the slew rate of a
tangent line to the actual signal from the DC level to V_REF (DC) level is used for de-rating value (see the figure of Slew Rate
Definition Tangent).
Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached V_IH / V_IL (AC) at
the time of the rising clock transition) a valid input signal is still required to complete the transition and reach V_IH / V_IL (AC).
For slew rates in between the values listed in the tables below, the de-rating values may be obtained by linear interpolation. These
values are typically not subject to production test. They are verified by design and characterization.
Elite Semiconductor Memory Technology Inc.
Publication Date : Aug. 2013
Revision : 1.3
20/64