M14D1G1664A-2D Datasheet, PDF (18/64 Pages) Elite Semiconductor Memory Technology Inc. – Internal pipelined double-data-rate architecture; two data access per clock cycle

ESMT
M14D1G1664A (2D)
6. t_HP is the minimum of the absolute half period of the actual input clock. t_HP is an input parameter but not an input
specification parameter. It is used in conjunction with t_QHS to derive the DRAM output timing t_QH. The value to be used for t_QH
calculation is determined by the following equation;
t_HP = Min ( t_CH (abs), t_CL (abs) ), where:
t_CH (abs) is the minimum of the actual instantaneous clock HIGH time;
t_CL (abs) is the minimum of the actual instantaneous clock LOW time;
7. t_QHS accounts for:
a. The pulse duration distortion of on-chip clock circuits, which represents how well the actual t_HP at the input is
transferred to the output; and
b. The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next transition, both
of which are independent of each other, due to data pin skew, output pattern effects, and p-channel to n-channel
variation of the output drivers.
8. t_QH = t_HP - t_QHS, where:
t_HP is the minimum of the absolute half period of the actual input clock; and t_QHS is the specification value under the max
column. {The less half-pulse width distortion present, the larger the t_QH value is; and the larger the valid data eye will be.}
Examples:
a. If the system provides t_HP of 1315 ps into a DDR2-667 SDRAM, the DRAM provides t_QH of 975 ps minimum.
b. If the system provides t_HP of 1420 ps into a DDR2-667 SDRAM, the DRAM provides t_QH of 1080 ps minimum.
9. RU stands for round up. WR refers to the t_WR parameter stored in the MRS.
10. ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on.
ODT turn on time max is when the ODT resistance is fully on. Both are measured from t_AOND.
11. ODT turn off time min is when the device starts to turn off ODT resistance.
ODT turn off time max is when the bus is in high impedance. Both are measured from t_AOFD.
12. For t_AOFD of DDR2-667/800/1066, the 1/2 clock of t_CK in the 2.5 x t_CK assumes a t_CH (avg), average input clock HIGH pulse
width of 0.5 relative to t_CK (avg). t_AOF (min.) and t_AOF (max.) should each be derated by the same amount as the actual
amount of t_CH (avg) offset present at the DRAM input with respect to 0.5.
For example, if an input clock has a worst case t_CH (avg) of 0.48, the t_AOF (min.) should be derated by subtracting 0.02 x t_CK
(avg) from it, whereas if an input clock has a worst case t_CH (avg) of 0.52, the t_AOF (max.) should be derated by adding 0.02 x
t_CK (avg) to it. Therefore, we have;
t_AOF (min.)(derated) = t_AC (min.) - [0.5 - Min(0.5, t_CH (avg)(min.))] x t_CK (avg)
t_AOF (max.)(derated) = t_AC (max.) + 0.6 + [Max(0.5, t_CH (avg)(max.)) - 0.5] x t_CK (avg) or
t_AOF (min.)(derated) = Min(t_AC (min.), t_AC (min.) - [0.5 - t_CH (avg)(min.)] x t_CK (avg))
t_AOF (max.)(derated) = 0.6 + Max(t_AC (max.), t_AC (max.) + [t_CH (avg)(max.) - 0.5] x t_CK (avg)), where:
t_CH (avg)(min.) and t_CH (avg)(max.) are the minimum and maximum of t_CH (avg) actually measured at the DRAM input balls.
Elite Semiconductor Memory Technology Inc.
Publication Date : Aug. 2013
Revision : 1.3
18/64