M12L2561616A_1 Datasheet, PDF (6/45 Pages) Elite Semiconductor Memory Technology Inc. – 4M x 16 Bit x 4 Banks Synchronous DRAM

ESMT
M12L2561616A
Parameter
Symbol
Col. address to col. address delay t_CCD(min)
Number of valid
Output data
CAS latency = 3
CAS latency = 2
Version
-6
-7
1
2
1
Unit
t_CK
ea
Note
3
4
Note : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then
rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
5. A new command may be given t_RFC after self refresh exit.
6. A maximum of eight consecutive AUTO REFRESH commands (with t_RFCmin) can be posted to any given SDRAM, and the
maximum absolute interval between any AUTO REFRESH command and the next AUTO REFRESH command is
8x7.8 μ s.)
AC CHARACTERISTICS (AC operating condition unless otherwise noted)
Parameter
-6
Symbol
-7
Unit
MIN MAX MIN MAX
CLK cycle time
CAS latency = 3
6
7
t_CC
1000
1000
ns
CAS latency = 2
10
10
CLK to valid
output delay
CAS latency = 3
-
5.4
-
5.4
t_SAC
ns
CAS latency = 2
-
5.4
-
5.4
Output data
hold time
CAS latency = 3
2.5
-
3
-
t_OH
ns
CAS latency = 2
-
-
3
-
CLK high pulsh width
t_CH
2.5
-
2.5
-
ns
CLK low pulsh width
t_CL
2.5
-
2.5
-
ns
Input setup time
t_SS
1.5
-
1.5
-
ns
Input hold time
t_SH
1
-
1
-
ns
CLK to output in Low-Z
t_SLZ
1
-
1
-
ns
CLK to output
in Hi-Z
CAS latency = 3
-
5.4
-
5.4
t_SHZ
ns
CAS latency = 2
-
6
-
6
Note :
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns. (tr/2 - 0.5) ns should be considered.
3. Assumed input rise and fall time (tr & tf) =1ns.
If tr & tf is longer than 1ns. transient time compensation should be considered.
i.e., [(tr + tf)/2 – 1] ns should be added to the parameter.
Note
1
1,2
2
3
3
3
3
2
-
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2008
Revision: 1.4
6/45