M12L2561616A_1 Datasheet, PDF (20/45 Pages) Elite Semiconductor Memory Technology Inc. – 4M x 16 Bit x 4 Banks Synchronous DRAM

ESMT
6. Precharge
M12L2561616A
1)Normal Write (BL=4)
CLK
CMD
WR
DQ
D0 D1 D2 D3
tRDL
*Note1
PRE
.
7. Auto Precharge
2)Normal Read (BL=4)
CLK
CMD
RD
DQ(CL2)
PRE CL=2
*Note2
Q0 Q1 Q2 Q3
CMD
DQ(CL3)
PRE CL=3
*Note2
Q0 Q1 Q2 Q3
1)Normal Write (BL=4)
2)Normal Read (BL=4)
CLK
CLK
CMD
WR
CMD
RD
DQ
D0 D1 D2 ^D3
tRDL (min)
DQ(CL2)
*Note3
Auto Precharge starts
DQ(CL3)
D0 D1 D2 D3
D0 ^D1 D2 ^D3
*Note3
Auto Precharge starts
*Note :
1. t_RDL : Last data in to row precharge delay.
2. Number of valid output data after row precharge : 1,2 for CAS Latency = 2,3 respectively.
3. The row active command of the precharge bank can be issued after t_RP from this point.
The new read/write command of other activated bank can be issued from this point.
At burst read/write with auto precharge, CAS interrupt of the same/another bank is illegal.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2008
Revision: 1.4
20/45