M12L2561616A_1 Datasheet, PDF (17/45 Pages) Elite Semiconductor Memory Technology Inc. – 4M x 16 Bit x 4 Banks Synchronous DRAM

ESMT
3. CAS Interrupt (I)
M12L2561616A
*N ote1
1)R ea d i nter ru pted by R ead (BL =4)
CL K
C MD
RD RD
ADD
A
B
DQ (CL2)
QA0 QB0 QB1 QB2 QB3
DQ( CL3)
t C CD
*Not e 2
QA0 QB0 QB1 QB2 QB3
2) Wr i te i n ter ru pte d b y W ri te (B L= 2)
CLK
C MD
ADD
DQ
WR WR
t CC D *No te 2
A
B
D A0 DB0 D B1
tC D L
*No te 3
3 )W ri te in ter rup ted by R ead (B L=2 )
DQ (C L2)
DQ( CL3)
WR RD
tC CD *N ote 2
A
B
DA0
DB0 DB1
DA0
tC D L
*No te 3
DB0 DB1
*Note : 1. By “interrupt” is meant to stop burst read/write by external before the end of burst.
By ” CAS interrupt ”, to stop burst read/write by CAS access ; read and write.
2. t_CCD : CAS to CAS delay. (=1CLK)
3. t_CDL : Last data in to new column address delay. (=1CLK)
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2008
Revision: 1.4
17/45