M12L2561616A_1 Datasheet, PDF (5/45 Pages) Elite Semiconductor Memory Technology Inc. – 4M x 16 Bit x 4 Banks Synchronous DRAM

ESMT
M12L2561616A
AC OPERATING TEST CONDITIONS (V_DD = 3.3V ± 0.3V ，T_A = 0 to 70 °C )
Parameter
Value
Unit
Input levels (Vih/Vil)
2.4/0.4
V
Input timing measurement reference level
1.4
V
Input rise and fall-time
tr/tf = 1/1
ns
Output timing measurement reference level
1.4
V
Output load condition
See Fig. 2
(Fig. 1) DC Output Load Circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Parameter
Symbol
Row active to row active delay
RAS to CAS delay
Row precharge time
Row active time
Row cycle time
@ Operating
@ Auto refresh
Last data in to col. address delay
Last data in to row precharge
Last data in to burst stop
Refresh period (8,192 rows)
t_RRD(min)
t_RCD(min)
t_RP(min)
t_RAS(min)
t_RAS(max)
t_RC(min)
t_RFC(min)
t_CDL(min)
t_RDL(min)
t_BDL(min)
t_REF(max)
(Fig. 2) AC Output Load Circuit
Version
-6
-7
12
14
18
20
18
20
42
45
100
60
63
60
70
1
2
1
64
Unit
ns
ns
ns
ns
us
ns
ns
t_CK
t_CK
t_CK
ms
Note
1
1
1
1
1
1,5
2
2
2
6
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2008
Revision: 1.4
5/45