M12L2561616A_1 Datasheet, PDF (19/45 Pages) Elite Semiconductor Memory Technology Inc. – 4M x 16 Bit x 4 Banks Synchronous DRAM

ESMT
M12L2561616A
(b) CL =3 ,B L= 4
CLK
i)CMD
DQM
DQ
ii)CMD
DQM
DQ
iii)CMD
DQM
DQ
iv)CMD
DQM
DQ
v)CMD
DQM
DQ
RD WR
D0 D1 D2 D3
RD
WR
D0 D1 D2 D3
RD
WR
D0 D1 D2 D3
RD
WR
Hi-Z
D0 D1 D2 D3
RD
WR
Hi-Z
Q0
D0 D1 D2 D3
*Note1
*Note : 1. To prevent bus contention, there should be at least one gap between data in and data out.
5. Write Interrupted by Precharge & DQM
CLK
CMD
DQM
DQ
WR
* N ot e 3
PRE
*No te 2
D0 D1 D2 D3
tR D L ( m in ) _{M a s k e d b y D Q M}
*Note :
1. To prevent bus contention, DQM should be issued which makes at least one gap between data in and data out.
2. To inhibit invalid write, DQM should be issued.
3. This precharge command and burst write command should be of the same bank, otherwise it is not precharge interrupt
but only another bank precharge of four banks operation.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2008
Revision: 1.4
19/45