M12L2561616A_1 Datasheet, PDF (13/45 Pages) Elite Semiconductor Memory Technology Inc. – 4M x 16 Bit x 4 Banks Synchronous DRAM

ESMT
COMMANDS
Mode register set command
( CS , RAS , CAS , WE = Low)
The M12L2561616A has a mode register that defines how the device operates.
In this command, A0~A12, BA0 and BA1 are the data input pins. After power on, the
mode register set command must be executed to initialize the device.
The mode register can be set only when all banks are in idle state.
During 2CLK following this command, the M12L2561616A cannot accept any
other commands.
M12L2561616A
CLK
CKE
H
CS
RAS
CAS
WE
BA0, BA1
A10
Add
Fig. 1 Mode register set
command
Activate command
( CS , RAS = Low, CAS , WE = High)
The M12L2561616A has four banks, each with 4,096 rows.
This command activates the bank selected by BA1 and BA0 (BS) and a row
address selected by A0 through A12.
This command corresponds to a conventional DRAM’s RAS falling.
CLK
CKE
H
CS
RAS
CAS
WE
BA0, BA1
(Bank select)
A10
Add
Row
Row
Fig. 2 Row address strobe and
bank active command
Precharge command
( CS , RAS , WE = Low, CAS = High )
This command begins precharge operation of the bank selected by BA1 and BA0
(BS). When A10 is High, all banks are precharged, regardless of BA1 and BA0.
When A10 is Low, only the bank selected by BA1 and BA0 is precharged.
After this command, the M12L2561616A can’t accept the activate command to
the precharging bank during t_RP (precharge to activate command period).
This command corresponds to a conventional DRAM’s RAS rising.
CLK
CKE
H
CS
RAS
CAS
WE
BA0, BA1
(Bank select)
A10
(Precharge select)
Add
Fig. 3 Precharge command
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2008
Revision: 1.4
13/45