M12L2561616A_1 Datasheet, PDF (30/45 Pages) Elite Semiconductor Memory Technology Inc. – 4M x 16 Bit x 4 Banks Synchronous DRAM

ESMT
M12L2561616A
Read & Write Cycle at Same Bank @ Burst Length = 4
0
1
2
3
4
5
6
7
8
9
10
11 12
13
14 15 16 17
18
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CLOCK
CKE
CS
RAS
CAS
tRCD
*Note1
tRC
HIGH
*Note2
ADDR
Ra
Ca
Rb
Cb
BA0
BA1
A10/AP
Ra
Rb
CL =2
DQ
CL =3
WE
Qa0 Qa1 Qa2 Qa3
*Note3
Qa0 Qa1 Qa2 Qa3
*Note3
Db0 Db1 Db2 Db3
tRDL
Db0 Db1 Db2 Db3
tRDL
DQM
Row Active
( A - Bank )
Read
( A - Bank )
Precharge
( A - Bank )
Row Active
( A - Bank )
Write
( A - Bank )
Precharge
(A - Bank)
:Don't Care
*Note :
1. Minimum row cycle times is required to complete internal DRAM operation.
2. Row precharge can interrupt burst on any cycle. [CAS Latency-1] number of valid output data is available after Row
precharge. Last valid output will be Hi-Z (t_SHZ) after the clock.
3. Output will be Hi-Z after the end of burst. (1,2,4,8 & Full page bit burst)
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2008
Revision: 1.4
30/45