M12L2561616A_1 Datasheet, PDF (21/45 Pages) Elite Semiconductor Memory Technology Inc. – 4M x 16 Bit x 4 Banks Synchronous DRAM

ESMT
8. Burst Stop & Interrupted by Precharge
M12L2561616A
CLK
1)Write Burst Stop (BL=8)
CMD
WR
STOP
DQM
DQ
D0 D1 D2 D3 D4 D5
tBDL ^*Note1
CLK
CMD
DQM
1)Write interrupted by precharge (BL=4)
WR
tRDL
*Note3
PRE
*Note4
DQ
D0 D1 Mask Mask
CLK
2)Read Burst Stop (BL=4)
CMD
RD
STOP
DQ(CL2)
*Note2
Q0 Q1
DQ(CL3)
*Note2
Q0 Q1
CLK
CMD
2)Read interrupted by precharge (BL=4)
*Note5
RD
PRE
DQ(CL3)
Q0 Q1 Q2 Q3
DQ(CL2)
Q0 Q1 Q2 Q3
9. MRS
1)Mod e Reg ister Set
CLK
CMD
*Note4
PRE
MRS
ACT
tRP
2CLK
*Note:
1. t_BDL : 1 CLK ; Last data in to burst stop delay.
Read or write burst stop command is valid at every burst length.
2. Number of valid output data after burst stop : 1,2 for CAS latency = 2,3 respectiviely.
3. Write burst is terminated. t_BDL determinates the last data write.
4. DQM asserted to prevent corruption of locations D2 and D3.
5. Precharge can be issued here or earlier (satisfying t_RAS min delay) with DQM.
6. PRE : All banks precharge, if necessary.
MRS can be issued only at all banks precharge state.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2008
Revision: 1.4
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