M12L2561616A_1 Datasheet, PDF (22/45 Pages) Elite Semiconductor Memory Technology Inc. – 4M x 16 Bit x 4 Banks Synchronous DRAM

ESMT
10. Clock Suspend Exit & Power Down Exit
M12L2561616A
1)Cl ock Su sp en d (=Act ive Power Down )Exit
CLK
CKE
Internal
CLK
*Note1
CMD
tSS
RD
CLK
2)Power Down (=Precharge Power Down)
CKE
tSS
Internal
CLK
CMD
*Note2
NOP ACT
11. Auto Refresh & Self Refresh
1)Auto Refresh & Self Refresh
*Note3
CLK
*Note4
CMD
PRE
AR
CKE
tRP
2)Self Refresh
CLK
CMD
*Note4
PRE
*Note6
SR
CKE
tRFC
tRP
*Note5
CMD
CMD
tRFC
*Note :
1. Active power down : one or more banks active state.
2. Precharge power down : all banks precharge state.
3. The auto refresh is the same as CBR refresh of conventional DRAM.
No precharge commands are required after auto refresh command.
During t_RFC from auto refresh command, any other command can not be accepted.
4. Before executing auto/self refresh command, all banks must be idle state.
5. MRS, Bank Active, Auto/Self Refresh, Power Down Mode Entry.
6. During self refresh entry, refresh interval and refresh operation are performed internally.
After self refresh entry, self refresh mode is kept while CKE is low.
During self refresh entry, all inputs expect CKE will be don’t cared, and outputs will be in Hi-Z state.
For the time interval of t_RFC from self refresh exit command, any other command can not be accepted.
Before/After self refresh mode, burst auto refresh (8192 cycles) is recommended.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2008
Revision: 1.4
22/45