M12L2561616A_1 Datasheet, PDF (15/45 Pages) Elite Semiconductor Memory Technology Inc. – 4M x 16 Bit x 4 Banks Synchronous DRAM

ESMT
Self refresh entry command
( CS , RAS , CAS , CKE = Low , WE = High)
After the command execution, self refresh operation continues while CKE
remains low. When CKE goes to high, the M12L2561616A exits the self refresh
mode.
During self refresh mode, refresh interval and refresh operation are performed
internally, so there is no need for external control.
Before executing self refresh, all banks must be precharged.
Burst stop command
( CS , WE = Low, RAS , CAS = High)
This command terminates the current burst operation.
Burst stop is valid at every burst length.
M12L2561616A
CLK
CKE
CS
RAS
CAS
WE
BA0, BA1
(Bank select)
A10
Add
Fig. 7 Self refresh entry
command
CLK
CKE
H
CS
RAS
CAS
WE
BA0, BA1
(Bank select)
A10
Add
Fig. 8 Burst stop command
No operation
( CS = Low, RAS , CAS , WE = High)
This command is not an execution command. No operations begin or terminate
by this command.
CLK
CKE
H
CS
RAS
CAS
WE
BA0, BA1
(Bank select)
A10
Add
Fig. 9 No operation
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2008
Revision: 1.4
15/45