M12L2561616A_1 Datasheet, PDF(2/45 Page) Elite Semiconductor Memory Technology Inc.

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M12L2561616A_1 Datasheet, PDF (2/45 Pages) Elite Semiconductor Memory Technology Inc. – 4M x 16 Bit x 4 Banks Synchronous DRAM

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ESMT

BLOCK DIAGRAM

CLK

CKE

Clock

Generator

Address

Mode

RAS

CAS

Row

Address

Buffer

Refresh

Counter

Column

Address

Buffer

Counter

M12L2561616A

Bank D

Bank C

Bank B

Bank A

Sense Amplifier

Column Decoder

Data Control Circuit

L(U)DQM

PIN DESCRIPTION

CLK

CKE

A0 ~ A12

BA1, BA0

RAS

CAS

L(U)DQM

DQ0 ~ DQ15

VDD / VSS

VDDQ / VSSQ

N.C

NAME

System Clock

Chip Select

Clock Enable

Address

Bank Select Address

Row Address Strobe

Column Address Strobe

Write Enable

Data Input / Output Mask

Data Input / Output

Power Supply / Ground

Data Output Power / Ground

No Connection

INPUT FUNCTION

Active on the positive going edge to sample all inputs

Disables or enables device operation by masking or enabling all

inputs except CLK , CKE and L(U)DQM

Masks system clock to freeze operation from the next clock cycle.

CKE should be enabled at least one cycle prior new command.

Disable input buffers for power down in standby.

Row / column address are multiplexed on the same pins.

Row address : RA0~RA12, column address : CA0~CA8

Selects bank to be activated during row address latch time.

Selects bank for read / write during column address latch time.

Latches row addresses on the positive going edge of the CLK with

RAS low. (Enables row access & precharge.)

Latches column address on the positive going edge of the CLK with

CAS low. (Enables column access.)

Enables write operation and row precharge.

Latches data in starting from CAS , WE active.

Makes data output Hi-Z, tSHZ after the clock and masks the output.

Blocks data input when L(U)DQM active.

Data inputs / outputs are multiplexed on the same pins.

Power and ground for the input buffers and the core logic.

Isolated power supply and ground for the output buffers to provide

improved noise immunity.

This pin is recommended to be left No Connection on the device.

Elite Semiconductor Memory Technology Inc.

Publication Date: Jun. 2008

Revision: 1.4

2/45

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