M12L2561616A_1 Datasheet, PDF (39/45 Pages) Elite Semiconductor Memory Technology Inc. – 4M x 16 Bit x 4 Banks Synchronous DRAM

ESMT
M12L2561616A
Active/Precharge Power Down Mode @ CAS Latency = 2, Burst Length = 4
0
1
CLOCK
2
3
4
5
6
7
8
9
10 11 12 13 14
15 16 17
18 19
CKE
HIGH
CS
RAS
CAS
ADDR
RAa
CAa
CAb
BA0
BA1
A10/AP
RAa
DQ
DAa0 DAa1 DAa2 DAa3 DAa4
tBDL
DAb0 DAb1 DAb2 DAb3 DAb4 DAb5
tRDL
*Note1
WE
DQM
Row Active
(A-Bank)
Write
(A-Bank)
Burst Stop
W rit e
(A-Bank)
Precharge
(A-Bank)
:Don't Care
*Note: 1. Both banks should be in idle state prior to entering precharge power down mode.
2. CKE should be set high at least 1CLK + t_SS prior to Row active command.
3. Can not violate minimum refresh specification.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2008
Revision: 1.4
39/45