E981.03 Datasheet, PDF (44/51 Pages) ELMOS Semiconductor AG – Autonomous MAC and individual physical address

KNX/ EIB TRANSCEIVER
PRODUCTION DATA - JAN 15, 2015
E981.03
Table 51. UART control register
back to Table 8 Register Table
UART_CTRL
content
hard reset value
soft reset value
access
bit description
MSB
LSB
-
-
-
TXDEL CRC
-
ON1
ON0
0
0
0
0
0
0
1
1
-
-
-
0
0
-
1
1
R
R
R
R/W ¹⁾
R/W ¹⁾
R
R/W ¹⁾
R/W ¹⁾
TXDEL:
"1": activate constant transmission delay between end of UART service and start of trans-
mission on KNX bus
"0": transmission delay between end of UART service and start of transmission on EIB bus
is variable (faster)
CRC:
"1": the UART CRC is enabled (not available in analog mode and not at 9.6kBd)
"0": the UART CRC is disabled
ON1 :
ON0 :
"-1" or "1-": the UART is switched on
"00": the UART is switched off
1) Access via UART service and SPI possible. In case of hard or soft reset the register is reset to the hard reset value or soft reset
value respectively.
1. The bit ON is doubled for safety reasons.
UART interface is switched off only if both ON bits have value "0".
Otherwise UART interface is switched on and the ON bits are set to value "1" by the E981.03 itself.
2. Bits ON1 and ON0 can not be modified using U_WriteReg service request.
Use SPI to switch UART on and off.
Bits TXDEL and CRC can be modified using either U_WriteReg service request or SPI.
3. Bit CRC is used to activate CRC calculation on UART to host communication. CRC is not used in case of KNX
bus monitor mode or 9.6 k baud UART speed, independent on the value of the CRC bit of register UART_CTRL.
Table 52. UART status register
back to Table 8 Register Table
UART_STAT
content
hard reset value
soft reset value
access
bit description
MSB
LSB
-
-
-
-
-
-
-
ON
0
0
0
0
0
0
0
0
- (not reset)
R
R
R
R
R
R
R
R ¹⁾
ON :
"1": the UART interface is currently on
"0": the UART interface is currently off. This may be because of Analog Mode activation or
because of a host write access to the UART_CTRL register
1) Access via UART service and SPI possible. In case of hard reset the register is reset to the hard reset value.
UART Byte Receiver
The parity bit of every received byte from the host will be checked by the E981.03. Errors will be reported to the
host controller by sending a State.indication service with receiver error flag set to the host as soon as possible.
The UART receiver accepts frames up to a maximum baud rate deviation of 3%. The signals can be transmitted
without a break.
Table 53. UART receiver registers
Register Name
UART_RX
Address
0x2A3
Description
previous received byte
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet
QM-No.: 25DS0046E.03
44/51