E981.03 Datasheet, PDF (42/51 Pages) ELMOS Semiconductor AG – Autonomous MAC and individual physical address

KNX/ EIB TRANSCEIVER
PRODUCTION DATA - JAN 15, 2015
E981.03
Table 42. Status of the transmit telegram buffer
back to Table 8 Register Table
KNX_TR_BUF_
STAT
content
hard reset value
soft reset value
access
bit description
MSB
LSB
-
-
-
-
-
-
-
READY
0
0
0
0
0
0
0
0
-
-
-
-
-
-
-
0
R
R
R
R
R
R
R
R/W ¹⁾
READY :
"1": the RAM buffer is ready for transmission
"0": the RAM buffer is not yet ready for transmission
The bit is set by either the host processor or internal logic and reset after successful trans-
mission. A manual write is only necessary if the frame is uploaded by SPI
1) Access via UART service and SPI possible. For write access read the remarks of every bit carefully. In case of hard or soft reset
the register is reset to the hard reset value or soft reset value respectively.
Table 43. Length of the frame in the transmit buffer (bit 8)
back to Table 8 Register Table
KNX_TX_LEN1 MSB
LSB
content
-
-
-
-
-
-
-
LEN8
hard reset value 0
0
0
0
0
0
0
0
soft reset value -
-
-
-
-
-
-
0
access
R
R
R
R
R
R
R
R/W ¹⁾
1) Access via UART service and SPI possible. If a frame is uploaded by SPI the host controller have to set the LEN bits. In case of hard
or soft reset the register is reset to the hard reset value or soft reset value respectively.
Table 44. Length of the frame in the transmit buffer (bits 7 ... 0)
back to Table 8 Register Table
KNX_TX_LEN0 MSB
LSB
content
hard reset value
soft reset value
access
LEN7
0
0
R/W ¹⁾
LEN6
0
0
R/W ¹⁾
LEN5
0
0
R/W ¹⁾
LEN4
0
0
R/W ¹⁾
LEN3
0
0
R/W ¹⁾
LEN2
0
0
R/W ¹⁾
LEN1
0
0
R/W ¹⁾
LEN0
0
0
R/W ¹⁾
1) Access via UART service and SPI possible. If a frame is uploaded by SPI the host controller have to set the LEN bits. In case of hard
or soft reset the register is reset to the hard reset value or soft reset value respectively.
Table 45. Acknowledge state register
Register Name
ACK_HOST
ACK_KNXIC
Address
0x21A
0x3E9
Description
acknowledge information from host
acknowledge information from E981.03
Table 46. Acknowledge information from host
back to Table 8 Register Table
ACK_HOST
content
hard reset value
soft reset value
external access
bit description
MSB
-
-
-
-
RX_ACK NACK BUSY
0
0
0
0
0
0
0
-
-
-
-
-
-
-
R
R
R
R
R/W ¹⁾
R/W ¹⁾
R/W ¹⁾
RX_ACK:„1": acknowledge information from host for frame currently received
"0": no acknowledge information from host for frame currently received
Bit is set by host access via SPI or UART and reset by internal logic at
start of a frame on KNX line.
NACK : not acknowledge flag
BUSY : busy flag
ADR : addressed flag
all flags are reset by the E981.03 at the beginning of a received frame.
LSB
ADR
0
-
R/W ¹⁾
1) Access via UART service and SPI possible. If a frame is uploaded by SPI the host controller have to set the LEN bits. In case of hard
reset the register is reset to the hard reset value.
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet
QM-No.: 25DS0046E.03
42/51