E981.03 Datasheet, PDF (40/51 Pages) ELMOS Semiconductor AG – Autonomous MAC and individual physical address

KNX/ EIB TRANSCEIVER
PRODUCTION DATA - JAN 15, 2015
E981.03
Table 37. Clock divider register (high part)
back to Table 8 Register Table
CLK_FAC1
MSB
LSB
content
F7
F6
F5
F4
F3
F2
F1
F0
hard reset value 1
1
1
0
0
0
1
1
soft reset value
access
1
R/W ¹⁾
1
R/W ¹⁾
1
R/W ¹⁾
0
R/W ¹⁾
0
R/W ¹⁾
0
R/W ¹⁾
1
R/W ¹⁾
1
R/W ¹⁾
1) Access via UART service and SPI possible. For write access read the remarks of every bit carefully. In case of hard or soft reset the
register is reset to the hard reset value or soft reset value respectively.
The clock divider has a total reset value of 58.254.
When using other quartz frequencies than 7.3728 MHz
the value has to be changed to
D_Q = f_Quartz / 126.76532 Hz - 1
Before changing the clock divider register values the
timing unit of the E981.03 runs with the accuracy of
the RC oscillator. Communication using the host UART
interface has to take that accuracy into account. Speci-
fied UART and KNX communication parameter ranges
are not guaranteed before adaption of the clock divider
register.
The PLL has a tolerance of approximately 10% to input
frequency for locking. As a result quartz frequencies
in the range between f_{Quartz, nom} – 10% and f_{Quartz, nom} +
10% may be regarded as the nominal quartz frequen-
cy resulting in incorrect timing at the KNX and UART
interfaces. It is highly recommended not to use quartz
frequencies in that range or to change the CLK_FAC reg-
isters using SPI after each reset of the E981.03.
Individual Node Address
Each KNX device has a unique individual address in a
network. The individual address is a 2 byte value that
consists of an 8 bit subnetwork address and an 8 bit
device address. The device address may have any value
between 0 and 255.
The individual node address can be uploaded to the
E981.03 from host using
• service request U_SetAddress on UART interface
(see chapter 7.1 UART-Service Host -> UART ) or writ-
ing to the appropriate RAM addresses (see chapter
7.3 SPI Logical Layer for details) and validate the ad-
dress by writing to the KNX_ADR_STAT register.
After upload address evaluation in E981.03 is activated.
After both hard and soft reset the address evaluation of
E981.03 is deactivated.
The device address shall be unique within a sub-net-
work.
The device address in E981.03 is not initialized to a defined value.
MSB
KNX subnet adress _{A3 A2 A1 A0}
high byte (0x108)
area adress
LSB
L3
L2
L1
L0
line adress
KNX subnet adress _{D7 D6 D5 D4 D3 D2 D1 D0}
low byte (0x109)
device adress
Figure 16. KNX individual address
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet
QM-No.: 25DS0046E.03
40/51