E981.03 Datasheet, PDF (32/51 Pages) ELMOS Semiconductor AG – Autonomous MAC and individual physical address

KNX/ EIB TRANSCEIVER
PRODUCTION DATA - JAN 15, 2015
E981.03
9 E981.03 security functions
The E981.03 has two security functions featuring an external digital interface.
SAVE
OTEMP
In case of an invalid VST voltage, the E981.03 activates the Save Mode to expand an active VCC time.
The SAVE pin gives this status of the Save Mode to an external device (host processor).
The temperature supervision is necessary for protection in case of higher power dissipation in failure
cases, for example short circuit of supply outputs. The OTEMP pin gives an over-temperature warning
10 RAM and register table
10.1 RAM table
Table 7. RAM address ranges
Address
0x000 ... 0x107
0x108 ... 0x109
0x10A ... 0x10B
0x10C
0x10D
0x10E ... 0x10F
0x110 ... 0x128
0x129 ... 0x12F
0x130 ... 0x148
0x149 ... 0x14F
0x150 ... 0x168
0x169 ... 0x16A
0x16B ... 0x16C
0x16D ... 0x1BF
0x1C0 ... 0x1FF
0x200 ... 0x2FF
0x300 ... 0x3FF
Bytes
264
2
2
1
1
2
25
7
25
7
25
2
2
82
64
256
256
Content
transmit frame buffer
individual KNX address of the KNX/EIB node
polling address ¹⁾
polling slot ¹⁾
polling data ¹⁾
reserved for E981.03 internal use ²⁾
alarm telegram buffer
reserved for E981.03 internal use ²⁾
trigger telegram buffer
reserved for E981.03 internal use ²⁾
trigger mask buffer
length of alarm telegram
length of trigger telegram
reserved for E981.03 internal use ²⁾
received frame buffer ²⁾
registers table ³⁾
registers table ^{2) 3)}
1) May be written by the host during a L_PollData.request frame.
2) Writing to these addresses is not allowed
3) Only allowed access to the named registers, see table below (register table).
App. note
10.2 Register table
Table 8. Register Table
Register Name
CMODE
RESET_CTRL
BUSY_REG
SPI_CTRL
SPI_PINS
UART_CTRL
CLK_CTRL
CLK_FAC0
CLK_FAC1
PS_CTRL
Address
0x200
0x201
0x202
0x205
0x206
0x208
0x209
0x20A
0x20B
0x20E
Description
communication mode
Reset control register
Busy Mode register
SPI control register
SPI pin access
UART control register
host clock control register
lower 8 bit of the clock divider register
upper 8 bit of the clock divider register
power supply control register
App. note
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet
QM-No.: 25DS0046E.03
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