E981.03 Datasheet, PDF (39/51 Pages) ELMOS Semiconductor AG – Autonomous MAC and individual physical address

KNX/ EIB TRANSCEIVER
PRODUCTION DATA - JAN 15, 2015
E981.03
Table 32. Set up the maximum bus current slope
back to Table 8 Register Table
CURRENT_SLOPE MSB
LSB
content
-
-
-
-
-
-
SL1
SL0
hard reset value 0
0
0
0
0
0
0
1
soft reset value
-
-
-
-
-
-
0
1
access
R
R
R
R
R
R
R/W ¹⁾ R/W ¹⁾
bit description see following table for SL values.
1) Access via UART service and SPI possible. For write access read the remarks of every bit carefully. In case of hard or soft reset the
register is reset to the hard reset value or soft reset value respectively.
Table 33. Bus current slope selection values
SL1
SL0
Slope limitation mode, mA/ms
0
0
0.25
0
1
0.5 (default)
1
0
1.25
1
1
2.5
Table 34. Clock registersSet up the maximum bus current slope
Register Name
CLK_CTRL
CLK_FAC0
CLK_FAC1
Address
0x209
0x20A
0x20B
Description
host clock control register
lower 8 bit of the clock divider register
upper 8 bit of the clock divider register
Table 35. Host clock control register
back to Table 8 Register Table
CLK_CTRL
MSB
LSB
content
-
-
-
-
-
EXT_Q -
ENQ
hard reset value 0
0
0
0
0
0
0
1
soft reset value
-
-
-
-
-
0
-
1
access
R
R
R
R
R
W ¹⁾
R
R/W ¹⁾
bit description
EXT_Q :
„1“: XTAL is used as clock input from external clock source, EXTAL is left open and internal
capacitors are disconnected
„0“: a quartz is connected to XTAL and EXTAL
ENQ :
„1“: crystal or clock enabled
„0“: crystal or clock disabled and XTAL grounded useful e.g. for analog mode
1) For write access read the remarks of every bit carefully. In case of soft and hard reset the state machine writes mentioned values.
Table 36. Clock divider register (low part)
CLK_FAC0
content
hard reset value
soft reset value
access
MSB
F7
0
0
R/W ¹⁾
F6
0
0
R/W ¹⁾
F5
1
1
R/W ¹⁾
F4
1
1
R/W ¹⁾
F3
0
0
R/W ¹⁾
back to Table 8 Register Table
F2
0
0
R/W ¹⁾
F1
0
0
R/W ¹⁾
LSB
F0
0
0
R/W ¹⁾
1) Access via UART service and SPI possible. For write access read the remarks of every bit carefully. In case of hard or soft reset the
register is reset to the hard reset value or soft reset value respectively.
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet
QM-No.: 25DS0046E.03
39/51