BCM4319XKUBGT Datasheet, PDF (78/84 Pages) Cypress Semiconductor – Single-Chip IEEE 802.11™ a/b/g/n MAC/Baseband/ Radio with Integrated SDIO and USB Interfaces

BCM4319 Preliminary Data Sheet
SDIO High Speed Mode Timing
Table 29: SDIO Bus Timing ^a Parameters (High-Speed Mode)
Parameter
Symbol Minimum Typical
SDIO CLK (all values are referred to minimum VIH and maximum VIL^b)
Frequency – Data Transfer Mode
fPP
0
–
Frequency – Identification Mode
Clock low time
fOD
0
–
tWL
7
–
Clock high time
tWH
7
–
Clock rise time
Clock low time
tTLH
–
–
tTHL
–
–
Inputs: CMD, DAT (referenced to CLK)
Input setup Time
tISU
6
–
Input hold Time
tIH
2
–
Outputs: CMD, DAT (referenced to CLK)
Output delay time – Data Transfer Mode
tODLY –
–
Output hold time
Total system capacitance (each line)
tOH
2.5
–
CL
–
–
a. Timing is based on CL ≤ 40pF load on CMD and Data.
b. min(Vih) = 0.7 × VDDIO_SD and max(Vil) = 0.2 × VDDIO_SD.
Maximum Unit
50
MHz
400
kHz
–
ns
–
ns
3
ns
3
ns
–
ns
–
ns
14
ns
–
ns
40
pF
Broadcom^®
April 2, 2014 • 4319-DS05-R
Single-Chip IEEE 802.11™ a/b/g/n MAC/Baseband/Radio
Page 77