BCM4319XKUBGT Datasheet, PDF (34/84 Pages) Cypress Semiconductor – Single-Chip IEEE 802.11™ a/b/g/n MAC/Baseband/ Radio with Integrated SDIO and USB Interfaces

BCM4319 Preliminary Data Sheet
gSPI
SPI Host-Device Handshake
To initiate communication through the SPI after power-up, the Host needs to bring up the WLAN/Chip by writing
to the Wake-up WLAN register bit. Writing a 1 to this bit will start up the necessary crystals and PLLs so that the
BCM4319 is ready for data transfer. The device can signal an interrupt to the Host indicating that the device is
awake and ready. This procedure also needs to be followed for waking up the device in sleep mode. The device
can interrupt the Host using the WLAN IRQ line whenever it has any information to pass to the Host. On getting
an interrupt, the Host needs to read the interrupt and/or status register to determine the cause of interrupt and
then take necessary actions.
Boot-Up Sequence
After power-up, the SPI Host needs to wait for the device to be out of reset. For this, the Host needs to poll with
a read command to F0 addr 0x14. Address 0x14 contains a predefined bit pattern. As soon as the Host gets a
response back with the correct register content, it implies that the device has powered up and is out of reset.
After that, the Host needs to set wakeup-wlan bit (F0 reg 0x00 bit 7). Wakeup-wlan issues a clock request to the
PMU.
For the first time after power-up, the Host needs to wait for the availability of low power clock inside the device.
Once that is available, the host needs to write to a PMU register to set the crystal frequency. This will turn on
the PLL. After the PLL is locked, chipActive interrupt is issued to the Host. This indicates device awake/ready
status. See Table 3 for information on SPI registers.
In Table 3, the following notation is used for register access:
• R: Readable from Host and CPU
• W: Writable from Host
• U: Writable from CPU
Address Register
x0000 Word length
Endianess
High speed mode
Interrupt polarity
Wake-up
x0001 Response delay
Table 3: SPI Registers
Bit Access Default Description
0 R/W/U 0
0 – 16 bit word length
1 – 32 bit word length
1 R/W/U 0
0 – Little Endian
1 – Big Endian
4 R/W/U 1
0 – Normal mode. RX and TX at different
edges.
1 – High speed mode. RX and TX on same
edge (default).
5 R/W/U 1
0 – Interrupt active polarity is low
1 – Interrupt active polarity is high (default)
7 R/W 0
A write of 1 will denote wake-up command
from Host to device. This will be followed by a
F2 Interrupt from SPI device to Host, indicating
device awake status.
7:0 R/W/U 8‘h04
Configurable read response delay in multiples
of 8 bits
Broadcom^®
April 2, 2014 • 4319-DS05-R
Single-Chip IEEE 802.11™ a/b/g/n MAC/Baseband/Radio
Page 33