BCM4319XKUBGT Datasheet, PDF (12/84 Pages) Cypress Semiconductor – Single-Chip IEEE 802.11™ a/b/g/n MAC/Baseband/ Radio with Integrated SDIO and USB Interfaces

BCM4319 Preliminary Data Sheet
List of Figures
List of Figures
Figure 1: BCM4319 System Block Diagram ...................................................................................................... 1
Figure 2: BCM4319 Block Diagram ................................................................................................................. 14
Figure 3: Mobile Phone System Diagram ........................................................................................................ 15
Figure 4: Power Topology Example................................................................................................................. 18
Figure 5: Recommended Oscillator Configuration ........................................................................................... 22
Figure 6: Recommended TCXO Connection ................................................................................................... 22
Figure 7: USB 2.0 Device Block Diagram ........................................................................................................ 26
Figure 8: Host Interface ................................................................................................................................... 28
Figure 9: SPI Write Protocol ............................................................................................................................ 29
Figure 10: SPI Read Protocol .......................................................................................................................... 29
Figure 11: SPI Command Structure................................................................................................................. 30
Figure 12: SPI Signal Timing Without Status................................................................................................... 31
Figure 13: SPI Signal Timing with Status (Response Delay = 0)..................................................................... 32
Figure 14: WLAN MAC Architecture ................................................................................................................ 36
Figure 15: WLAN PHY Block Diagram............................................................................................................. 40
Figure 16: STBC Receive Block Diagram........................................................................................................ 41
Figure 17: Radio Functional Block Diagram .................................................................................................... 42
Figure 18: Signal Connections to SDIO Card (SD 4-Bit Mode) ....................................................................... 55
Figure 19: Signal Connections to SDIO Card (gSPI Mode) ............................................................................. 55
Figure 20: RF Port Location............................................................................................................................. 60
Figure 21: Power-Up Sequence Timing Diagram ............................................................................................ 73
Figure 22: gSPI Timing .................................................................................................................................... 74
Figure 23: SDIO Bus Timing (Default Mode) ................................................................................................... 75
Figure 24: SDIO Bus Timing (High-Speed Mode)............................................................................................ 76
Figure 25: 138-Ball WLBGA Mechanical Information ...................................................................................... 81
Broadcom^®
April 2, 2014 • 4319-DS05-R
Single-Chip IEEE 802.11™ a/b/g/n MAC/Baseband/Radio
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