BCM4319XKUBGT Datasheet, PDF (38/84 Pages) Cypress Semiconductor – Single-Chip IEEE 802.11™ a/b/g/n MAC/Baseband/ Radio with Integrated SDIO and USB Interfaces

BCM4319 Preliminary Data Sheet
MAC Features
PSM
The programmable state machine (PSM) is a microcode engine that provides most of the low-level hardware
control for implementing the 802.11 specification. It is a microcontroller that is highly optimized for flow control
operations, which are predominant in implementations of communication protocols. The instruction set and
fundamental operations are simple and general, which allows algorithms to be optimized late in the design
process. It also allows algorithm changes to track evolving 802.11 specifications.
The PSM fetches instructions from the microcode memory. It uses shared memory to obtain operands for
instructions and to exchange data between both the host and the MAC data pipeline (via the SHM bus). The
PSM also uses a scratchpad memory, similar to a register bank, to store frequently accessed and temporary
variables.
The PSM exercises fine grained control over the hardware engines by programming Internal Hardware
Registers (IHRs). These IHRs are colocated with the hardware functions they control, and are accessed by the
PSM via the IHR bus.
The PSM fetches instructions from the microcode memory using an address determined by the program
counter, instruction literal, or a program stack. For arithmetic and logic unit (ALU) operations, the operands are
obtained from shared memory, scratchpad memory, IHRs, or instruction literals, and the results are written into
the shared memory, scratchpad memory, or IHRs.
There are two basic branch instructions: conditional branches and ALU-based branches. To better support the
many decision points in the 802.11 algorithms, branches can depend on either readily available signals from the
hardware modules (branch condition signals are available to the PSM without polling the IHRs) or on the results
of ALU operations.
WSE
TheWireless Security Engine (WSE) encapsulates all the hardware accelerators to perform encryption,
decryption, and message integrity check (MIC) computation and verification. The accelerators implement the
legacy WEP, WPA TKIP, and WPA2™ AES-CCMP cipher algorithms.
The PSM determines the appropriate cipher algorithm to use based on frame type and association information.
It supplies the keys to the hardware engines from an on-chip key table. WSE interfaces with the transmit engine
(TXE) to encrypt and compute the MIC on transmit frames and the receive engine (RXE) to decrypt and verify
the MIC on receive frames.
TXE
The TXE constitutes the transmit data path of the MAC. It coordinates the DMA engines to store the transmit
frames in the TXFIFO. It interfaces with the WSE module to encrypt frames, and transfers the frames across
the MAC-PHY interface at the appropriate time determined by the channel access mechanisms.
The data received from the DMA engines are stored in transmit FIFOs. The MAC supports multiple logical
queues to support traffic streams that have different Quality of Service (QoS) priority requirements. The PSM
uses the channel access information from the interframe spacing (IFS) module to schedule a queue from which
the next frame is transmitted. Once the frame is scheduled, the TXE hardware transmits the frame based on a
precise timing trigger received from the IFS module.
Broadcom^®
April 2, 2014 • 4319-DS05-R
Single-Chip IEEE 802.11™ a/b/g/n MAC/Baseband/Radio
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