BCM4319XKUBGT Datasheet, PDF (77/84 Pages) Cypress Semiconductor – Single-Chip IEEE 802.11™ a/b/g/n MAC/Baseband/ Radio with Integrated SDIO and USB Interfaces

BCM4319 Preliminary Data Sheet
SDIO High Speed Mode Timing
Table 28: SDIO Bus Timing ^a Parameters (Default Mode) (Cont.)
Parameter
Symbol Minimum Typical
Inputs: CMD, DAT (referenced to CLK)
Input setup time
Input hold time
tISU
5
–
tIH
5
–
Outputs: CMD, DAT (referenced to CLK)
Output delay time – Data Transfer mode
tODLY 0
–
Output delay time – Identification mode
tODLY 0
–
a. Timing is based on CL ≤ 40pF load on CMD and Data.
b. min(Vih) = 0.7 × VDDIO_SD and max(Vil) = 0.2 × VDDIO_SD.
Maximum Unit
–
ns
–
ns
14
ns
50
ns
SDIO High Speed Mode Timing
SDIO high speed mode timing is shown by the combination of Figure 24 and Table 29.
Figure 24: SDIO Bus Timing (High-Speed Mode)
50% VDD
f_PP
t_WL
t_WH
SDIO_CLK
Input
t_THL
t_TLH
t_ISU
t_IH
Output
t_ODLY
t_OH
Broadcom^®
April 2, 2014 • 4319-DS05-R
Single-Chip IEEE 802.11™ a/b/g/n MAC/Baseband/Radio
Page 76