BCM4319XKUBGT Datasheet, PDF (18/84 Pages) Cypress Semiconductor – Single-Chip IEEE 802.11™ a/b/g/n MAC/Baseband/ Radio with Integrated SDIO and USB Interfaces

BCM4319 Preliminary Data Sheet
• PALDO: 2.7–5.5V in; 2.7–4.0V, 400 mA out
• LDO2p5V: 2.7 – 5.5V in; 2.5V, 50 mA out for USB2.0 Phy
Power Supply Topology
Power Supply Topology
The BCM4319 contains power supply building blocks, including a switching regulator, four LDOs, and a power
amplifier LDO (see Figure 4 on page 18). These blocks simplify power supply design for WLAN in embedded
designs. All regulator inputs and outputs are brought out to pins on the BCM4319, thereby enabling maximum
system design flexibility in choosing which of the integrated regulators to use.
A single host power supply, ranging from 2.7V to 5.5V, can be used with all additional voltages being provided
by BCM4319 regulators. For additional information see Section 12: “Internal Regulator Electrical Specifications,”
on page 68. Alternately, if specific rails such as 3.3V, 2.5V, and 1.2V already exist in the system, appropriate
regulators in the BCM4319 can be disabled, thereby reducing the cost and board space associated with external
regulator components such as inductors and large capacitors.
When WL_REG_ON is low (< 1.2 – 20% = 0.96V) or the voltage at VDDIO is less than 0.96V, all six regulators
are powered down.
When WL_REG_ON is high (> 1.6V) and the voltage at VDDIO is greater than 1.6V, the CBUCK, LDO2p5V,
CLDO, and LNLDO1 regulators are powered on by default. The digital logic remains in the reset state while
EXT_POR_L is low or while the internal POR is asserted. The internal POR circuit generates a reset within 110
ms after VDDC and VDDIO stabilize. After the resets are deasserted, the BCM4319 powers up the PALDO,
OTP, and clock circuitry.
After the digital logic is active and the software is running, the state of all the regulators is controlled dynamically.
To keep the digital logic powered up, CBUCK and CLDO cannot be powered down. They can, however, be put
into low-power modes. The PALDO can be powered ON or OFF under software control to reduce power
consumption, for example during sleep mode.
There is a 200 KΩ (±20%) internal pull-down on WL_REG_ON, which can be disabled after the digital logic is
active.
• The voltage at WL_REG_ON should not exceed 3.6V.
• The IO supply for the EXT_POR_L pin is VDDIO.
• VBAT and VDDIO should be supplied externally: VDDIO cannot be supplied by the output of any of the six
regulators.
• The POR delays are different for the three IO supplies:
• VDDIO = 110 ms
• VDDIO_SD = 8 us
• VDDIO_RF = 3.4 ms
The trip point of the internal POR circuit is VDDC ~ 0.8V or VDDIO/VDDIO_SD/VDDIO_RF ~ 0.9V and the IOs
remain in tristate during the respective POR.
Broadcom^®
April 2, 2014 • 4319-DS05-R
Single-Chip IEEE 802.11™ a/b/g/n MAC/Baseband/Radio
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