BCM4319XKUBGT Datasheet, PDF (51/84 Pages) Cypress Semiconductor – Single-Chip IEEE 802.11™ a/b/g/n MAC/Baseband/ Radio with Integrated SDIO and USB Interfaces

BCM4319 Preliminary Data Sheet
Signal Descriptions
Table 6: 138-Ball WLBGA Signal Descriptions (Cont.)
Ball
Signal Name
WJ7
AMODE_EXT_LNA_PU
WJ8
AMODE_EXT_LNA_GAIN
Integrated LDOs
WN5
VDD_CLDO
WN6
WL7
WP5
WP6
WL8
VDD_LNLDO1
VDD_LNLDO2
VOUT_CLDO
VOUT_LNLDO1
VOUT_LNLDO2
WM6
VREF_LDO
WP9
SR_AVDD2P5
Type
O
O
I
I
I
O
O
O
O
O
WN7
SR_PALDO
O
WP7
SR_PALDO
O
WM7
SR_PNPO
O
WL9
SR_TESTSWG
O
WN8
SR_VDDBAT3
I
WP8
SR_VDDBAT3
I
WP10 SR_VDDNLDO
O
Integrated Switching Regulator
WL10 SR_VDDBAT1
I
WL11 SR_VDDBAT1
I
WN9
SR_VDDBAT2
I
WM11 SR_VLX1
O
WN11 SR_VLX1
O
WP11 SR_VSSPLDO
I
SDIO Bus Interface* (IO supply = VDDIO_SD)
WE11 SDIO_CMD
I/O
WJ11
SDIO_DATA_0
I/O
WH11 SDIO_DATA_1
I/O
WG11 SDIO_DATA_2
I/O
WF8
SDIO_DATA_3
I/O
WK11 SDIO_CLK
I/O
Description
Enable signal for optional external 802.11a LNA.
Control signal for optional external 802.11a LNA.
Input supply pin for CLDO: also functions as the feedback
pin for the CBUCK switching regulator
Input supply pin for LNLDO1
Input supply pin for LNLDO2 (backup linear regulator)
1.2V output for core LDO, 200 mA
1.2V output for low noise LNLDO1, 150 mA
1.2V or 2.5V–3.1V programmable output for low noise
LNLDO2, 50 mA
Vref bypass: Connect external decoupling capacitor to
ground.
2.5V LDO2p5 output: used for various internal BCM4319
blocks in addition to the USB PHY: the output capacitor is
required even when USB functionality is not used.
Internal PALDO output or feedback of output from external
PNP
Control output for PNP base
Test output for switcher/LDOs
Battery supply input for PALDO
NLDO reference pin output: Connect to 220 nF external
capacitor to ground. Do not use for other external circuits.
Core buck regulator: Battery voltage input
Core buck regulator: Output to inductor
–
Tracks battery voltage: Connect to 220 nF external
capacitor to battery.
SDIO command line
SDIO data line 0
SDIO data line 1
SDIO data line 2
SDIO data line 3
SDIO clock
Broadcom^®
April 2, 2014 • 4319-DS05-R
Single-Chip IEEE 802.11™ a/b/g/n MAC/Baseband/Radio
Page 50