BCM4319XKUBGT Datasheet, PDF (35/84 Pages) Cypress Semiconductor – Single-Chip IEEE 802.11™ a/b/g/n MAC/Baseband/ Radio with Integrated SDIO and USB Interfaces

BCM4319 Preliminary Data Sheet
gSPI
Table 3: SPI Registers (Cont.)
Address Register
Bit
x0002 Status enable
0
Interrupt with status
1
Response delay for all 2
x0003 Reserved
x0004 Interrupt register
0
x0005
x0006 -
x0007
x0008 -
x000B
x000C -
x000D
x000E -
x000F
x0010 -
x0011
x0014 -
x0017
1
2
5
6
7
Interrupt register
5
6
7
Interrupt enable register 15:0
Status register
31:0
F1 info register
0
1
13:2
F2 info register
0
1
15:2
F3 info register
0
1
15:2
Test–Read only register 31:0
x0018 - Test–R/W register
31:0
x001B
Access Default
R/W 1
R/W 0
R/W 0
Description
0 – No status sent to host after read/write
1 – Status sent to host after read/write
0 – Do not interrupt if status is sent
1 – Interrupt host even if status is sent
0 – Response delay applicable to F1 read only
1 – Response delay applicable to all function
read
R/W
R
R
R
R
R
R
R
R
R/W/U
R
0
Requested data not available; Cleared by
writing a 1 to this location
0
F2/F3 FIFO underflow due to last read
0
F2/F3 FIFO overflow due to last write
0
F2 packet available
0
F3 packet available
0
F1 overflow due to last write
0
F1 Interrupt
0
F2 Interrupt
0
F3 Interrupt
16'hE0E7 Particular Interrupt is enabled if a
corresponding bit is set
32'h0000 Same as status bit definitions
R
R
R/U
R/U
R
R/U
R/U
R
R/U
R
R/W/U
1
F1 enabled
0
F1 ready for data transfer
12'h40 F1 max packet size
1
F2 enabled
0
F2 ready for data transfer
14'h800 F2 max packet size
1
F3 enabled
0
F3 ready for data transfer
14'h800 F3 max packet size
32'hFEE This register contains a predefined pattern,
DBEAD which the host can read and determine if the
SPI interface is working properly.
32'h0000 This is a dummy register where the host can
0000
write some pattern and read it back to
determine if the SPI interface is working
properly.
Broadcom^®
April 2, 2014 • 4319-DS05-R
Single-Chip IEEE 802.11™ a/b/g/n MAC/Baseband/Radio
Page 34