BCM4319XKUBGT Datasheet, PDF (73/84 Pages) Cypress Semiconductor – Single-Chip IEEE 802.11™ a/b/g/n MAC/Baseband/ Radio with Integrated SDIO and USB Interfaces

BCM4319 Preliminary Data Sheet
Power-Up Sequence
Section 13: Power-Up Sequence
SDIO Host Timing Requirement
The SDIO host must wait a minimum of 150 ms after the VDDC (1.25V DC supply for core) ramps up and settles
before initiating access to the BCM4319. For typical designs, one of the BCM4319 internal regulators generates
VDDC: the regulators are enabled by WL_REG_ON going HIGH.
Reset and Regulator Control Signal Sequencing
The BCM4319 has two control signals that allow the host to control power consumption by enabling or disabling
the WLAN and internal regulator blocks. These control signals are as follows:
• WL_REG_ON: Can be used by a host CPU to power-up or power down the internal BCM4319 regulators.
• EXT_POR_L: Low asserting reset for the WLAN core. This pin needs to be driven high or low; it must not
be left floating. If EXT_POR_L is low, the BCM4319 core will be powered off.
WL_REG_ON and EXT_POR_L can be tied together.
The timing diagram shown in Figure 21 on page 73 is provided to indicate proper sequencing of the signals for
WLAN operation. The timing values indicated are minimum required values; longer delays are also acceptable.
Note: The timing diagram is not to scale and is only for illustration purposes.
Broadcom^®
April 2, 2014 • 4319-DS05-R
Single-Chip IEEE 802.11™ a/b/g/n MAC/Baseband/Radio
Page 72