BCM4319XKUBGT Datasheet, PDF (19/84 Pages) Cypress Semiconductor – Single-Chip IEEE 802.11™ a/b/g/n MAC/Baseband/ Radio with Integrated SDIO and USB Interfaces

BCM4319 Preliminary Data Sheet
Figure 4: Power Topology Example
VBAT 2.7V - 5.5V
VDDIO 1.8 to 3.3V
BCM4319
VDDIO and VDDIO_SD
BCM4319
LN LD01
Input: 1.4V
Output:1.2V 150 mA
(Optional)
LN LD02
Input: 1.4 or 3.3V
Output: 1.2 or 2.5-3.1V, 50 mA
1.2V
Core Buck Regulator
(300 mA)
1.4V
CLDO
Input: 1.4V
Output:1.2V 200 mA
1.2V
LDO2p5
2.5V 50 mA
PALDO
(3.3V, 400 mA)
NOTE: Shaded areas are internal to the BCM4319.
AFE: Analog front end
OTP: One-time programmable memory
PLL: Phase-locked loop
WL: Wireless LAN
PMU Sequencer
BCM4319
WL Radio
RF PLL
WL AFE
Xtal
Core Logic Blocks
WL Radio
(noise insensitive)
WL Digital
USB
USB 2.0 Phy, other
internal blocks
VDDIO_RF
WL OTP
Internal WLAN
Power Amplifier
USBPHY 3.3V
PMU Sequencer
The PMU sequencer is responsible for minimizing system power consumption. It enables and disables various
system resources based on a computation of the required resources and the relationship between resources
and their enable and disable times.
In each device state, a minimum set of resources is always available, as defined in the PMU control registers.
Additional resources can be enabled on request from various sources, including clock requests from cores and
timers in any of the active resources. The PMU sequencer maps clock requests into a set of resources required
to produce the requested clocks.
Broadcom^®
April 2, 2014 • 4319-DS05-R
Single-Chip IEEE 802.11™ a/b/g/n MAC/Baseband/Radio
Page 18