STC5455 Datasheet, PDF (9/56 Pages) Connor-Winfield Corporation – Synchronous Clock for SETS

STC5455
Synchronous Clock for SETS
Data sheet
Table 2: Register Map
Addr
0x2D
0x2E
0x2F
0x30
0x31
0x32
0x33
0x34
0x35
0x36
0x37
0x38
0x3C
0x3D
0x3E
0x3F
0x40
0x42
0x43
0x44
0x4A
0x4B
0x4C
0x4D
0x4E
0x4F
0x50
0x51
0x52
0x59
0x5A
0x5B
0x5C
0x5D
0x70
0x71
0x72
0x73
0x74
0x7F
Reg Name
Short_Term_Accu_History
User_Specified_History
History_Ramp
Ref_Priority_Table
PLL_Status
Holdover_Accu_Flush
PLL_Event_Out
PLL_Event_In
EX_SYNC_Edge_Config
Frame_Phase_Align
Synth_Index_Select
Synth_Freq_Value
Synth_Skew_Adj
CLK1_Signal_Level
CLK1_Sel
CLK2_Sel
Frame8K_Sel
Frame2K_Sel
Ref__Acceptable_Freq
Frame_Mux
Field_Upgrade_Status
Field_Upgrade_Data
Field_Upgrade_Count
Field_Upgrade_Start
MCLK_Freq_Reset
Bits
31-0
Type
R
Description
Short term Accumulated History
31-0 R/W User programmed holdover history
7-0
19-0
R/W
R/W
Control long term history and short term history accumulation band-
width and the locking stage’s frequency ramp control
REF1-5 selection priority
7-0
0
7-0
7-0
2-0
19-0
R
W
R/W
R/W
R/W
R/W
PLL status: SYNC, LOS, LOL, OOP, SAP, FEE, DHT, HHA
Flush/reset the long-term history and the device holdover history
PLL event out (Reserved)
PLL event in: Relock
Select framing edge (falling or rising edge) for EX_SYNC1/2/3
Selects frame reference input and sampling edge on selected refer-
ence for frame alignment. (T0 timing generator only)
3-0
17-0
11-0
0
1-0
1-0
6-0
6-0
14-0
1-0
2-0
7-0
12-0
R/W Select a synthesizer to access registers Synth_Freq_Value and
Synth_Skew_Adj
R/W Selects synthesizer frequency value from 1MHz to 156.25MHz, in
1kHz steps, based on which synthesizer index is selected at the reg-
ister Synth_Index_Select
R/W Adjust phase skew for the synthesizer with the index selected at
register Synth_Index_Select
R/W Select the signal level (LVDS or LVPECL) for clock outputs CLK1
R/W Select synthesizer or enable tri-state for CLK1
R/W Select synthesizer or enable tri-state for CLK2
R/W 8kHz frame pulse clock output duty cycle selection, signal inversion
R/W 2kHz frame pulse clock output duty cycle selection, signal inversion
R/W Select integer N for manually acceptable frequency at Nx8kHz;
Enable auto detection of reference input frequency
R/W Select one of frame signal (Frame8K, Frame2K) and forward it to
CLK2 selection
R Indicates the status of field upgrade process
R/W Load 7600 bytes of firmware configuration data
R Count byte numbers that have been loaded
7-0
W Write three values consecutively to start the field upgrade process
7-0 R/W Select the frequency of the external oscillator
Note 1: Timing generator T0 and T4 share register 0x20 ~ 0x3F. Register 0x1F selects between T0 and T4 for the sharing registers 0x20
~0x3F.
Preliminary
Page 9 of 56 TM121
Rev:P1.3
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: October 24, 2011