STC5455 Datasheet, PDF (37/56 Pages) Connor-Winfield Corporation – Synchronous Clock for SETS

Long_Term_Accu_History, 0x29 (R)
STC5455
Synchronous Clock for SETS
Data sheet
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x29
0x2A
0x2B
0x2C
Bits 0 - 7 of 32 bit Long Term History
Bits 8 - 15 of 32 bit Long Term History
Bits 16 - 23 of 32 bit Long Term History
Bits 24 - 31 of 32 bit Long Term History
Long term accumulated history relative to MCLK. 2’s complement. Resolution is 0.745x10^-3 ppb.
Short_Term_Accu_History, 0x2D (R)
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x2D
0x2E
0x2F
0x30
Bits 0 - 7 of 32 bit Short term History
Bits 8 - 15 of 32 bit Short term History
Bits 16 - 23 of 32 bit Short term History
Bits 24 - 31 of 32 bit Short term History
Short term accumulated history relative to MCLK. 2’s complement. Resolution is 0.745x10^-3 ppb.
User_Specified_History, 0x31 (R/W)
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x31
0x32
0x33
0x34
Bits 0 - 7 of 32 bit User Holdover History
Bits 8 - 15 of 32 bit User Holdover History
Bits 16 - 23 of 32 bit User Holdover History
Bits 24 - 31 of 32 bit User Holdover History
User specified history relative to MCLK. 2’s complement. Resolution is 0.745x10^-3 ppb.
Default value: 0
History_Ramp, 0x35 (R/W)
Address
0x35
Bit7
Bit6
Bit5
Bit4
Long Term History Accumulator Bandwidth
Bit3
Bit2
Short Term History Accu-
mulator Bandwidth
Holdover history accumulator bandwidth and ramp controls.
Bit1
Bit0
Ramp Control
Bits 7 ~ 4
0
1
2
3
4
Long Term
History -3dB
Bandwidth
4.9 mHz
2.5 mHz
1.2 mHz
0.62 mHz
0.31 mHz
Preliminary
Page 37 of 56 TM121
Rev:P1.3
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: October 24, 2011