STC5455 Datasheet, PDF (1/56 Pages) Connor-Winfield Corporation – Synchronous Clock for SETS

STC5455
Synchronous Clock for SETS
Data sheet
Description
Features
Functional Specification
The RoHS 6/6 compliant STC5455 is a single chip clock
synchronization solution for applications in SDH/SETS,
SONET, and Synchronous Ethernet network elements. The
device is fully compliant with ITU-T G.813 option 1 and 2,
G.8262 EEC option 1and 2, Telcordia GR1244 and GR253.
The STC5455 accepts 5 clock reference inputs, three exter-
nal frame sync inputs (EX_SYNC1, 2, 3) and generates 4
synchronized clock outputs. Synchronized outputs may be
programmed for wide variety of frequencies from 1MHz up
to 156.25MHz, in 1kHz steps. Reference inputs are individ-
ually monitored for activity and quality. Reference selection
may be automatic, manual, or hard-wired manual.
Two independent timing generators, T0 and T4, may oper-
ate in the Freerun, Synchronized, Pseudo Holdover, and
Holdover mode. Synchronization is operated in external
timing mode while freerun and holdover are operated in
self-timing mode. Each timing generator includes a DSP-
based PLL. DSP-based PLL technology removes any exter-
nal component except the oscillator. It provides excellent
performance and reliability to STC5455.
The STC5455 is clocked by an external oscillator (TCXO or
OCXO). Using a well-chosen external oscillator ensures the
STC5455 meet the required specifications and standards.
- Complies with ITU-T G.813 opt1/2, G.8262 EEC opt1/2,
Telcordia GR1244 and GR253 (Stratum3/4E/4/SMC)
- Two timing generators, T0 and T4; T4 locks indepen-
dently or locks to T0
- Supports Multiple-Master redundant application (T0 tim-
ing generator only)
- Accepts external oscillator at frequency of 10MHz,
12.8MHz, 19.2MHz, or 20MHz with programming
- Accepts 5 clock reference inputs
- Provides three 2kHz or 8kHz external frame sync inputs
- Each reference input is monitored for activity and quality
- Supports automatic frequency detection or manually
acceptable frequency.
- Automatic, manual, and hard-wired manual reference
selection
- Outputs 4 synchronized clock outputs, including 2 frame
pulse outputs
- 4 programmable clock synthesizers
- Phase-align locking or hit-less reference switching
- Programmable loop bandwidth, from 0.1Hz to 100Hz
- Programmable phase skew in synthesizer level
- SPI bus interface
- Single 3.3V operation
- IEEE 1149.1 JTAG boundary scan
- Available in TQFP 64 package
SRCSW
EX_SYNC 1
EX_SYNC 2
EX_SYNC 3
Ref Clk
5
3 LVCMOS
+
2 LVPECL/LVDS
TCXO
OCXO
T0 Timing
Generator
Ref
Monitor
Synth Frame8K
F
Frame2K
Synthesizer G₁
1MHz ~ 156.25MHz
Synthesizer G₂
1MHz ~ 156.25MHz
T4 Timing
Generator
Synthesizer G_T4
2.048MHz
SPI Interface
Figure 1:Functional Block Diagram
CLK8K
CLK2K
CLK1, LVPECL/LVDS
CLK2
Preliminary
Page 1 of 56 TM121 Rev: P1.3
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: October 24, 2011