STC5455 Datasheet, PDF (16/56 Pages) Connor-Winfield Corporation – Synchronous Clock for SETS

Control Interfaces
Controls interfaces of the STC5455 are composed of
hardwire control pins and the SPI bus interface. They
provide application access to the internal control and
status registers.
Field Upgradability
The STC5455 supports field upgradability which
allows the user to load size of 7600 byte firmware
configuration data (provided as per request) via bus
interface. It provides the user a flexible field solution
for different applications.
Advantage and Performance
The kernel of each timing generator is a DSP-based
PLL. In STC5455, all internal modules are either digi-
tal or numerical, including the phase detectors, filters,
and clock synthesizers. The revolutionary pure-digital
design makes the timing generator become an accu-
rate and reliable deterministic system. This modern
technology removes any external component except
the external oscillator. It provides excellent perfor-
mance and reliability to STC5455.
A well-chosen oscillator demanded to meet all the
synchronization requirements. Short-term stability
with respect to the desired loop bandwidth is a more
important factor than aging projection and thermal
response when an appropriate oscillator is selected.
STC5455
Synchronous Clock for SETS
Data sheet
Functional Specification
Preliminary
Page 16 of 56 TM121 Rev: P1.3
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: October 24, 2011