STC5455 Datasheet, PDF (32/56 Pages) Connor-Winfield Corporation – Synchronous Clock for SETS

Reference activity indicator.
0 = inactive, 1 = active
Default value: 0
Refs_Qual, 0x18 (R)
STC5455
Synchronous Clock for SETS
Data sheet
Address
Bit7
Bit6
Bit5
0x18
Not Used
Reference qualification indicator.
0 = not qualified, 1 = qualified.
Default value: 0
Interrupt_Event_Status, 0x1A (R/W)
Bit4
Ref 5
Bit3
Ref 4
Bit2
Ref 3
Bit1
Ref 2
Bit0
Ref 1
Address
0x1A
Bit7
Event 7
Bit6
Event 6
Bit5
Event 5
Bit4
Event 4
Bit3
Event 3
Bit2
Event 2
Bit1
Event 1
Bit0
Event 0
Event0: Reference qualification status
0 = no change, 1 = reference qualification status changed.
Event1: Reserved
Event2: T0 selected reference in auto-selection mode
0= no change, 1 = T0 selected reference changed
Event3: T0 PLL status
0= no change, 1 = T0 PLL status changed
Event4: T0 timing generator’s event out
0= no event out, 1= any of T0 PLL event out is asserted or not cleared at the register of
PLL_Event_Out
Event5: T4 selected reference in auto-selection mode
0= no change, 1 = T4 selected reference changed
Event6: T4 PLL status
0= no change, 1 = T0 PLL status changed
Event7: T4 timing generator’s event out
0= no event out, 1= any of T4 PLL event out is asserted or not cleared at the register of
PLL_Event_Out
Interrupts are cleared by writing “1” to the associated bit.
Default value: 0
Interrupt_Event_Enable, 0x1B (R/W)
Address
0x1B
Bit7
Event 7
Bit6
Event 6
Bit5
Event 5
Bit4
Event 4
Bit3
Event 3
Bit2
Event 2
Bit1
Event 1
Bit0
Event 0
Selects which of events will assert the pin EVENT_INTR to active state (See register Interrupt_Config).
Preliminary
Page 32 of 56 TM121
Rev:P1.3
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: October 24, 2011