STC5455 Datasheet, PDF (24/56 Pages) Connor-Winfield Corporation – Synchronous Clock for SETS

STC5455
Synchronous Clock for SETS
Data sheet
protection against single part failure.
Frame Reference Input
For multiple-master redundant design, all the timing
devices should keep in frame phase alignment. In
order to achieve the alignment, the frame edge of ref-
erence input is required. If the reference input is not
at frequency of 8kHz, an external frame sync input (at
pin EX_SYNC1/2/3) is used and some configuration
enhancements are required. See register Frame
Phase Align for configuration.
Multiple Master Configuration
In multiple-master configuration, each unit works as
master and locks to the same reference input. Each
unit has consistent loop bandwidth settings. To
achieve frame phase alignment for outputs of all the
masters, each device has to choose same frame
edge on the selected reference input. The system
may provides every master a common frame refer-
ence or simply choose a reference input at 8kHz.
Frame reference input and frame edge on each
selected reference input is configured at register
Frame Phase Align for Ref1~Ref5 respectively. If an
error occurs when sampled on the selected frame
edge of the selected reference, bit FEE of the register
PLL Status will be asserted and the frame pulse
clock output CLK8K will replace the selected frame
reference input as the temporary frame reference.
The error does not impact bit SYNC and LOL of the
register PLL Status. User can invoke a re-lock event
to PLL by programming the register PLL Event In
under this situation. The frame edge will be re-
selected as well.
Multiple master configuration works only in frame
phase align mode. By writing to the register Frame
Phase Align, user can set T0 timing generator to
frame phase align mode with the frame edge selec-
tion.
In order to meet the same synchronization and frame
alignment requirements, each unit should keep the
same parameter setup, especially loop bandwidth.
Multiple-master mode demands a high quality exter-
nal oscillator to obtain a precise frame phase align-
ment.
Event Interrupts
Functional Specification
The STC5455 events shown following below are
interrupt events might occurred.
- Qualification status of the reference inputs change
- Activity status of the cross reference inputs change
- Selected reference of timing generator T0 changes in
automatic reference selection
- Selected reference of timing generator T4 changes in
automatic reference selection
- PLL status of timing generator T0 changes
- PLL status of timing generator T4 changes
- Out-Event of timing generator T0 asserts
- Out-Event of timing generator T4 asserts
The interrupt events can be read from the register
Interrupt Status. Each bit indicates one events. The
associate bit of the register Interrupt Status will not
be changed automatically when the event is cleared.
Therefore, the user need write ‘1’ to the associate bit
to erase the event.
The STC5455 has a pin EVENT_ INTR (pin 8) for
indicating the event interrupt occurrence. The pin
may be wired to user’s micro-controller. User can pro-
gram the register Interrupt Mask to decide which of
interrupt events will send an alarm to the micro-con-
troller by asserting the EVENT_INTR pin. User can
program at the Interrupt Configuration register to
specify the logic level (active high or low) of the pin
EVENT_INTR when it’s trigged by the interrupt event.
User may also program the Interrupt Configuration
register to define pin states as tri-state or logic inac-
tive when no interrupt event occurs.
Field Upgradability
The STC5455 supports field upgradability which
allows the user to load size of 7600 byte firmware
configuration data (provided as per request) via bus
interface. Field upgrade can only be performed at
least 3ms after reset.
1. User may read Bit READY of the register Field
Upgrade Status to check if field upgrade is ready
to start.
Preliminary
2. To begin the field upgrade, write to register Field
Upgrade Start three times consecutively, with no
intervening read/writes from/to other registers, see
Page 24 of 56 TM121 Rev: P1.3
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: October 24, 2011