STC5455 Datasheet, PDF (2/56 Pages) Connor-Winfield Corporation – Synchronous Clock for SETS

STC5455
Synchronous Clock for SETS
Data sheet
Table of Contents
STC5455 Pin Diagram (Top View) .................................................................................................................... 5
STC5455 Pin Description .................................................................................................................................. 6
Register Map ..................................................................................................................................................... 8
Master Clock Frequency .................................................................................................................................. 10
Input and Output Frequencies ......................................................................................................................... 11
Input Frequencies .................................................................................................................................... 11
Auto-Detect Acceptable Input Frequencies ...................................................................................... 11
Manually Acceptable Input Frequencies .......................................................................................... 11
Clock Output Frequencies ....................................................................................................................... 12
Clock Output Jitter .......................................................................................................................................... 13
General Description ......................................................................................................................................... 14
Application ............................................................................................................................................... 14
Overview .................................................................................................................................................. 14
Chip Master Clock .................................................................................................................................... 14
Reference Inputs and External Sync Inputs ............................................................................................. 14
Reference Inputs .............................................................................................................................. 14
External Frame Sync Inputs ............................................................................................................. 14
Timing Generators and Operation Modes ................................................................................................ 15
Phase Synchronization ............................................................................................................................ 15
Clock Outputs .......................................................................................................................................... 15
Redundant Designs ................................................................................................................................. 15
Control Interfaces ..................................................................................................................................... 16
Field Upgradability ................................................................................................................................... 16
Advantage and Performance ................................................................................................................... 16
Detailed Description ......................................................................................................................................... 17
Chip Master Clock .................................................................................................................................... 17
Freerun Clock .......................................................................................................................................... 17
Operation Mode ....................................................................................................................................... 17
PLL Event In ............................................................................................................................................ 18
Frequency and Phase Transients ............................................................................................................ 18
Frequency Transients ....................................................................................................................... 18
Phase Transients ............................................................................................................................. 18
History of Fractional Frequency Offset .................................................................................................... 18
Short-Term History ........................................................................................................................... 18
Long-Term History ............................................................................................................................ 19
Device Holdover History ................................................................................................................... 19
User-Specified History ...................................................................................................................... 19
Phase-Locked Loop Status Details .......................................................................................................... 19
External SYNC Inputs and Reference Inputs Details ............................................................................... 20
External Frame Sync Inputs ............................................................................................................. 20
Acceptable Frequency and Frequency Offset Detection .................................................................. 20
Activity Monitoring ............................................................................................................................ 20
Input Qualification ............................................................................................................................ 21
Automatic Reference Election Mechanism ...................................................................................... 21
Automatic Reference Selection ........................................................................................................ 22
Manual Reference Selection Mode .................................................................................................. 22
Hard-wired Manual Reference Selection ......................................................................................... 22
Clock Outputs Details .............................................................................................................................. 22
Clock Synthesizers ........................................................................................................................... 22
Preliminary
Page 2 of 56 TM121
Rev:P1.3
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: October 24, 2011