STC5455 Datasheet, PDF (27/56 Pages) Connor-Winfield Corporation – Synchronous Clock for SETS

STC5455
Synchronous Clock for SETS
Data sheet
CS
t_CS
t_CSHLD
t_CSMIN
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
SCLK
t_Ds
t_Dh
t_CL
t_CH
SDI
0 ^{A0 A1 A2 A3 A4 A5 A6} D0 ^{D1 D2 D3} D4 ^{D5 D6 D7}
LSB
MSB LSB
MSB
Figure 10:SPI Bus Timing, Write access
Table 7: SPI Bus Timing
Symbol
Description
Min
Max
Unit
t_CS
CS low to SCLK high
10
ns
t_CH
SCLK high time
50
ns
t_CL
SCLK low time
50
ns
t_Ds
Data setup time
10
ns
t_Dh
Data hold time
10
ns
t_DRDY Data ready
7
ns
t_DHLD Data hold
3
ns
t_CSHLD CS hold
30
ns
t_CSTRI CS off to data tri-state
5
ns
t_CSMIN Minimum delay between successive accesses
50
ns
Preliminary
Page 27 of 56 TM121
Rev:P1.3
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: October 24, 2011