STC5455 Datasheet, PDF (33/56 Pages) Connor-Winfield Corporation – Synchronous Clock for SETS

0 = mask out, 1 = enable
STC5455
Synchronous Clock for SETS
Data sheet
Event0: Reference qualification status changed
Event1: Reserved
Event2: T0 selected reference changed in auto-selection mode
Event3: T0 PLL status changed
Event4: T0 timing generator’s event out is asserted
Event5: T4 selected reference changed in auto-selection mode
Event6: T4 PLL status changed
Event7: T4 timing generator’s event out is asserted
Default value: 0
Interrupt_Config, 0x1C (R/W)
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
0x1C
Not used
Signal active state
Specify the signal active state at pin EVENT_INTR
0 = active low. 1 = active high
Idle state
Specify the idle state of pin EVENT_INTR when no interrupt event occurs.
0 = tri-state. 1 = logic inactive
Default value: 0
Hard-wired_Switch_Pre_Selection, 0x1D (R/W)
Bit1
Idle state
Bit0
Signal active state
Address
0x1D
Bit7
Bit6
Bit5
Bit4
Pre-selected reference number 2
Bit3
Bit2
Bit1
Bit0
Pre-selected reference number 1
Pre select reference number 1 and reference number 2 in hard-wired manual reference selection mode. This
mode is controlled by pin SRCSW. When pin SRCSW is LOW, reference number 1 is pre-selected. When pin
SRCSW is HIGH, reference number 2 is pre-selected. It can be configured only when bit7 of Control_Mode
register is set to 1 (See register Control_Mode).
Default value: 0
Field Value
0
1~5
13
14~15
Selection
Freerun
Ref1~Ref5
Holdover
Reserved
Preliminary
Page 33 of 56 TM121
Rev:P1.3
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: October 24, 2011