STC5455 Datasheet, PDF (43/56 Pages) Connor-Winfield Corporation – Synchronous Clock for SETS

STC5455
Synchronous Clock for SETS
Data sheet
Phase skew adjust for synthesizer G₁, G₂, or F based on the selection at the register Synth_Index_Select.
Synthesizer G_T4 is not phase skew programmable. The adjustment is from -6400/128 ns to 6396.875/128
ns, which is -50ns ~ 49.976 ns, in 3.125/128 ns steps, 2’s complement.
Synthesizer Index Selection
Synthesizer F
Synthesizer G₁
Synthesizer G₂
Default value: 0 (For all the synthesizers)
CLK1_Signal_Level, 0x50 (R/W)
Associated CLK Output
CLK8K, CLK2K, CLK2
CLK1
CLK2
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x50
Not used
CLK1 Signal Level
Selects the signal level for clock outputs CLK1
0 = LVPECL, 1 = LVDS
Default value: 0
CLK1_Sel, 0x51(R/W)
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
0x51
Not used
Selects clock output CLK1 derived from synthesizer G₁ or put in tri-state.
Bit1
Bit0
CLK1 Synthesizer Select
Default value: 0
CLK2_Sel, 0x52 (R/W)
Bits 1 ~ 0
0, 2, 3
1
CLK1 Synthesizer Select
Put CLK1 in tri-state mode
Synthesizer G₁
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x52
Not used
CLK2 Synthesizer Select
Selects the clock output CLK2 derived from synthesizer G₂ (T0) or synthesizer G_T4(T4). Frame8K and
Frame2K are produced at synthesizer F. When synthesizer F is selected, sets bit1~bit0 of the register
Frame_Mux to select frame pulse clock Frame8K or Frame2K. Signal level of CLK2 is LVCMOS.
Register
Frame_Mux
(Bit1~Bit0)
Bits 1 ~ 0
CLK2 Synthesizer Select
X
0
Put CLK2 in tri-state mode
Preliminary
Page 43 of 56 TM121
Rev:P1.3
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: October 24, 2011