STC5455 Datasheet, PDF (15/56 Pages) Connor-Winfield Corporation – Synchronous Clock for SETS

STC5455
Synchronous Clock for SETS
Data sheet
Timing Generators and Operation
Modes
The STC5455 includes two independent timing gen-
erators, T0 and T4, to provide the essential functions
for SETS. Each timing generator can individually
operate in Freerun, Synchronized, Pseudo-Hold-
over and Holdover mode. A timing generator is in
either external-timing mode or self-timing mode. In
external timing mode, PLL of the timing generator
phase locks to the selected external reference input.
In self-timing mode, the PLL simply tunes the clock
synthesizers to a given fractional frequency offset.
Synchronized mode is in external timing. PLL’s loop
bandwidth may be programmed individually to vary
the timing generator’s filtering function. Conversely,
freerun, pseudo-holdover and holdover modes are all
in self-timing. When selected reference input and pre-
vious holdover history are unavailable, such as in
system’s initialization stage, freerun mode may be
entered or used. When selected reference input is
unavailable but a long-term holdover history accumu-
lated in previous synchronized mode is available,
holdover mode may be entered or used. STC5455
may enter pseudo-holdover using short-term fre-
quency history. In STC5455, the freerun clock is
derived from the MCLK (external oscillator) and digi-
tally calibrated to compensate the external oscillator’s
accuracy offset. STC5455 also allow users to pro-
gram and manipulate the holdover history accumula-
tors.
Phase Synchronization
In synchronized mode, the phase relationship
between the selected reference input and the clock
output may be phase arbitrary or frame phase align
for T0 timing generator. For timing generator T4, the
phase relationship is phase arbitrary only. Zero frame
phase relationship is produced for T0 timing genera-
tor by programming as frame phase align mode.
Switching to a new reference input may expect a
longer pull-in process in this mode. On the other
hand, programming as arbitrary mode, an arbitrary
phase relationship incorporates phase rebuild on ref-
erence input switching to minimize the downstream
clock’s phase transient. In this scenario, the STC5455
can provide hit-less switching if both reference inputs
are traced to the same clock source (e.g., PRC). The
STC5455 may accept external frame reference to
achieve frame alignment in frame phase align mode.
The frame reference and the frame edge, and frame
phase alignment mode may be configured indepen-
dently for each indiviFduuanl cretfieornenacleSinppeuct.ification
A maximum frequency ramp may be programmed to
minimize the ramp of fractional frequency offset
changing in the case that the new selected reference
is not traced to the same source. This feature
restrains the frequency transient which may cause
the pull-out-of lock of the downstream network ele-
ments.
Clock Outputs
The STC5455 outputs 4 synchronized clock outputs:
differential output CLK1(LVPECL or LVDS), LVCMOS
output CLK2, frame pulse clock outputs CLK8K at
8kHz and CLK2K at 2kHz (LVCMOS). CLK1 can be
derived from synthesizer G₁ through T0 path. CLK2
can be derived from synthesizer G₂ or F through T0
path and also can be derived from synthesizer G_T4
through T4 path. See Figure 1 for functional details.
Frequency of clock output CLK1 and CLK2 is pro-
grammable by programing frequency of the associ-
ated synthesizer from 1MHz up to 156.25MHz, in
1kHz steps. The STC5455 allows the user to program
the phase skew of each clock synthesizer except syn-
thesizer G_T4, up and down 50ns in roughly 0.024ns
step to adjust the phase of clock outputs.
Frame pulse clock synthesizer F generates frame
pulse clock Frame8K/Frame2K at frequency of 8kHz/
2kHz. The duty-cycle of Frame8K and Frame2K is
programmable. Clock outputs CLK8K and CLK2K are
directly driven from Frame8K and Frame2K.
Redundant Designs
Timing generator T0 supports multiple-master oper-
ation for redundant applications to allow system
protection against the failure of the single unit.
In multiple-master configuration, all units work as
masters and lock to the same reference input in paral-
lel. In phase align mode, with the selection of frame
reference inputs (EX_SYNC1/2/3) and the frame
edge, clock outputs of all the units may keep in frame
phase alignment. In order to meet same synchroniza-
tion requirement, each unit should use same parame-
ter setup including loop bandwidth. Multiple-master
configuration demands a high quality external oscilla-
tor to obtain a precise frame phase alignment.
Preliminary
Page 15 of 56 TM121 Rev: P1.3
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: October 24, 2011