SAMA5D41_14 Datasheet, PDF (995/1776 Pages) ATMEL Corporation – Atmel | SMART ARM-based Embedded MPU

• THALT: Transmit Halt
Writing one to this bit halts transmission as soon as any ongoing frame transmission ends.
• TXPF: Transmit Pause Frame
Writing one to this bit causes a pause frame to be transmitted.
• TXZQPF: Transmit Zero Quantum Pause Frame
Writing one to this bit causes a pause frame with zero quantum to be transmitted.
• SRTSM: Store Receive Time Stamp to Memory
0: Normal operation.
1: Causes the CRC of every received frame to be replaced with the value of the nanoseconds field of the 1588 timer that
was captured as the receive frame passed the message time stamp point.
• ENPBPR: Enable PFC Priority-based Pause Reception
Enables PFC Priority Based Pause Reception capabilities. Setting this bit enables PFC negotiation and recognition of pri-
ority-based pause frames.
• TXPBPF: Transmit PFC Priority-based Pause Frame
Takes the values stored in the Transmit PFC Pause Register.
• FNP: Flush Next Packet
Flush the next packet from the external RX DPRAM. Writing one to this bit will only have an effect if the DMA is not cur-
rently writing a packet already stored in the DPRAM to memory.
SAMA5D4 Series [DATASHEET]
Atmel-11238A-ATARM-SAMA5D4-Datasheet_30-Sep-14
995