SAMA5D41_14 Datasheet, PDF (483/1776 Pages) ATMEL Corporation – Atmel | SMART ARM-based Embedded MPU

30.7 Product Dependencies
30.7.1 I/O Lines
The pins used for interfacing the Static Memory Controller are multiplexed with the PIO lines. The programmer
must first program the PIO controller to assign the Static Memory Controller pins to their peripheral function. If I/O
lines of the SMC are not used by the application, they can be used for other purposes by the PIO controller.
30.7.2 Power Management
The SMC is clocked through the Power Management Controller (PMC), thus the programmer must first configure
the PMC to enable the SMC clock.
30.7.3 Interrupt
The SMC has an interrupt line connected to the interrupt controller. Handling the SMC interrupt requires
programming the interrupt controller before configuring the SMC.
Table 30-3. Peripheral IDs
Instance
ID
HSMC
22
30.8
External Memory Mapping
The SMC provides up to 26 address lines, A[25:0]. This allows each chip select line to address up to 64 Mbytes of
memory.
If the physical memory device connected on one chip select is smaller than 64 Mbytes, it wraps around and
appears to be repeated within this space. The SMC correctly handles any valid access to the memory device
within the page (see Figure 30-3).
A[25:0] is only significant for 8-bit memory; A[25:1] is used for 16-bit memory.
Figure 30-3. Memory Connections for External Devices
NCS[0] - NCS[3]
SMC
NRD
NWE
A[25:0]
D[15:0]
NCS3
Memory Enable
NCS2
Memory Enable
NCS1
Memory Enable
NCS0
Memory Enable
Output Enable
Write Enable
8 or 16
A[25:0]
D[15:0] or D[7:0]
SAMA5D4 Series [DATASHEET]
Atmel-11238A-ATARM-SAMA5D4-Datasheet_30-Sep-14
483