SAMA5D41_14 Datasheet, PDF (1518/1776 Pages) ATMEL Corporation – Atmel | SMART ARM-based Embedded MPU

47.7.43 PWM Channel Period Register
Name:
PWM_CPRDx [x=0..3]
Address: 0xF800C20C [0], 0xF800C22C [1], 0xF800C24C [2], 0xF800C26C [3]
Access:
Read/Write
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
CPRD
15
14
13
12
11
10
9
8
CPRD
7
6
5
4
3
2
1
0
CPRD
This register can only be written if bits WPSWS3 and WPHWS3 are cleared in the PWM Write Protection Status Register.
Only the first 16 bits (channel counter size) are significant.
• CPRD: Channel Period
If the waveform is left-aligned, then the output waveform period depends on the channel counter source clock and can be
calculated:
– By using the PWM peripheral clock divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32, 64,
128, 256, 512, or 1024). The resulting period formula will be:
f^-(-_p^-X--_e^--_r^-_i^×--_p^--_h^-C-_e^--_r^-P-_a^--_l^--R_c^---_l^-D_o^--_c^--_k^)-
– By using the PWM peripheral clock divided by one of both DIVA or DIVB divider, the formula becomes,
respectively:
(_---C_---f-R_-p--e-P_-r--i-pD_--h---e-×_-r-a--l-D_--c--l-I_o--V_c--k--A_----)_{- or} (_---C_---f-R_-p--e-P_-r--i-pD_--h---e-×_-r-a--l-D_--c--l-I_o--V_c---k-B_----)
If the waveform is center-aligned, then the output waveform period depends on the channel counter source clock and can
be calculated:
– By using the PWM peripheral clock divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32, 64,
128, 256, 512, or 1024). The resulting period formula will be:
(_---2--f--p×_--e--r-X_-i-p--h-×_--e--r-C_a--l---P_c--l-o-R_--c--D_k----)_-
– By using the PWM peripheral clock divided by one of both DIVA or DIVB divider, the formula becomes,
respectively:
(_---2----×_---f--C_p---e--P_r-i--p-R_-h--e-D_-r--a--l-×_-c--l-D_-o--c--I_k--V_----A_----)_{- or} (_---2----×_---f--C_p---e--P_r-i--p-R_-h--e-D_-r--a--l×_--c---lD_-o--c--I_k--V_----B_----)_-
1518
SAMA5D4 Series [DATASHEET]
Atmel-11238A-ATARM-SAMA5D4-Datasheet_30-Sep-14