SAMA5D41_14 Datasheet, PDF (1318/1776 Pages) ATMEL Corporation – Atmel | SMART ARM-based Embedded MPU

44.6.1.2 Fractional Baud Rate in Asynchronous Mode
The baud rate generator is subject to the following limitation: the output frequency changes only by integer
multiples of the reference frequency. An approach to this problem is to integrate a fractional N clock generator that
has a high resolution. The generator architecture is modified to obtain baud rate changes by a fraction of the
reference source clock. This fractional part is programmed with the FP field in the US_BRGR. If FP is not 0, the
fractional part is activated. The resolution is one eighth of the clock divider. This feature is only available when
using USART normal mode. The fractional baud rate is calculated using the following formula:
Baudrate
=
--------------^S---^e---^l--^e---^c---^t--^e---^d----^C----^l--^o---^c---^k--------------
^{8(2 – Over)}^{CD + F---8--P--}
The modified architecture is presented in the following Figure 44-3.
Figure 44-3. Fractional Baud Rate Generator
FP
USCLKS
MCK
0
MCK/DIV ₁
Reserved ₂
3
SCK
(CLKO = 0)
CD
Modulus
Control
16-bit Counter
FP
CD
Glitch-free
Logic
>1
1
0
0
0
1
SYNC
USCLKS = 3
FIDI
OVER
Sampling
Divider
SCK
(CLKO = 1)
SYNC
0
Baud Rate
Clock
1
Sampling
Clock
44.6.1.3 Baud Rate in Synchronous Mode or SPI Mode
If the USART is programmed to operate in Synchronous mode, the selected clock is simply divided by the field CD
in the US_BRGR.
BaudRate = ^S----^e---^l--^e---^c---^tC--^e---_Dd---^C-----^l--^o---^c---^k-
In Synchronous mode, if the external clock is selected (USCLKS = 3), the clock is provided directly by the signal on
the USART SCK pin. No division is active. The value written in US_BRGR has no effect. The external clock
frequency must be at least 3 times lower than the system clock. In Synchronous mode master (USCLKS = 0 or 1,
CLKO set to 1), the receive part limits the SCK maximum frequency tof_{peripheral clock}/3 in USART mode, or f_peripheral
clock^{/6 in SPI mode.}
When either the external clock SCK or the internal clock divided (peripheral clock/DIV) is selected, the value
programmed in CD must be even if the user has to ensure a 50:50 mark/space ratio on the SCK pin. When the
peripheral clock is selected, the baud rate generator ensures a 50:50 duty cycle on the SCK pin, even if the value
programmed in CD is odd.
1318
SAMA5D4 Series [DATASHEET]
Atmel-11238A-ATARM-SAMA5D4-Datasheet_30-Sep-14