SAMA5D41_14 Datasheet, PDF (1124/1776 Pages) ATMEL Corporation – Atmel | SMART ARM-based Embedded MPU

38.14.3 HSMCI Data Timeout Register
Name:
Address:
Access:
HSMCI_DTOR
0xF8000008 (0), 0xFC000008 (1)
Read/Write
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
8
–
–
–
–
–
–
–
–
7
6
5
4
3
2
1
0
–
DTOMUL
DTOCYC
This register can only be written if the WPEN bit is cleared in the HSMCI Write Protection Mode Register.
• DTOCYC: Data Timeout Cycle Number
This field determines the maximum number of Master Clock cycles that the HSMCI waits between two data block transfers.
It equals (DTOCYC x Multiplier).
• DTOMUL: Data Timeout Multiplier
Multiplier is defined by DTOMUL as shown in the following table:
Value
0
1
2
3
4
5
6
7
Name
1
16
128
256
1024
4096
65536
1048576
Description
DTOCYC
DTOCYC x 16
DTOCYC x 128
DTOCYC x 256
DTOCYC x 1024
DTOCYC x 4096
DTOCYC x 65536
DTOCYC x 1048576
If the data time-out set by DTOCYC and DTOMUL has been exceeded, the Data Time-out Error flag (DTOE) in the HSMCI
Status Register (HSMCI_SR) rises.
1124
SAMA5D4 Series [DATASHEET]
Atmel-11238A-ATARM-SAMA5D4-Datasheet_30-Sep-14