SAMA5D41_14 Datasheet, PDF (719/1776 Pages) ATMEL Corporation – Atmel | SMART ARM-based Embedded MPU

32.7.40 Overlay 1 Interrupt Status Register
Name:
LCDC_OVR1ISR
Address: 0xF0000158
Access:
Read-only
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
8
–
–
–
–
–
–
–
–
7
6
5
4
3
2
1
0
–
OVR
DONE
ADD
DSCR
DMA
–
–
• DMA: End of DMA Transfer
0: No End of Transfer has been detected since last read of LCDC_OVR1ISR
1: End of Transfer has been detected. This flag is reset after a read operation.
• DSCR: DMA Descriptor Loaded
0: No descriptor has been loaded since last read of LCDC_OVR1ISR
1: A descriptor has been loaded successfully. This flag is reset after a read operation.
• ADD: Head Descriptor Loaded
0: No descriptor has been loaded since last read of LCDC_OVR1ISR
1: The descriptor pointed to by the LCDC_OVR1HEAD register has been loaded successfully. This flag is reset after a read
operation.
• DONE: End of List Detected
0: No End of List condition has occurred since last read of LCDC_OVR1ISR
1: End of List condition has occurred. This flag is reset after a read operation.
• OVR: Overflow Detected
0: No overflow occurred since last read of LCDC_OVR1ISR
1: An overflow occurred. This flag is reset after a read operation.
SAMA5D4 Series [DATASHEET]
Atmel-11238A-ATARM-SAMA5D4-Datasheet_30-Sep-14
719