SAMA5D41_14 Datasheet, PDF (317/1776 Pages) ATMEL Corporation – Atmel | SMART ARM-based Embedded MPU

27.17.11 PMC Master Clock Register
Name:
PMC_MCKR
Address: 0xF0018030
Access:
Read/Write
31
30
29
28
27
26
–
–
–
–
–
–
23
22
21
20
19
18
–
–
–
–
–
–
15
14
13
12
11
10
–
–
–
PLLADIV2
–
–
7
6
5
4
3
2
–
PRES
–
–
• CSS: Master/Processor Clock Source Selection
Value Name
Description
0
SLOW_CLK
Slow Clock is selected
1
MAIN_CLK
Main Clock is selected
2
PLLA_CLK
PLLACK is selected
3
UPLL_CLK
UPLL Clock is selected
• PRES: Master/Processor Clock Prescaler
Value Name
Description
0
CLOCK
Selected clock
1
CLOCK_DIV2 Selected clock divided by 2
2
CLOCK_DIV4 Selected clock divided by 4
3
CLOCK_DIV8 Selected clock divided by 8
4
CLOCK_DIV16 Selected clock divided by 16
5
CLOCK_DIV32 Selected clock divided by 32
6
CLOCK_DIV64 Selected clock divided by 64
7
Reserved
Reserved
• MDIV: Master Clock Division
Value Name
Description
0
EQ_PCK
Master Clock is Prescaler Output Clock divided by 1.
WARNING: SysClk DDR and DDRCK are not available.
1
PCK_DIV2
Master Clock is Prescaler Output Clock divided by 2.
SysClk DDR is equal to 2 x MCK. DDRCK is equal to MCK.
2
PCK_DIV4
Master Clock is Prescaler Output Clock divided by 4.
SysClk DDR is equal to 2 x MCK. DDRCK is equal to MCK.
3
PCK_DIV3
Master Clock is Prescaler Output Clock divided by 3.
SysClk DDR is equal to 2 x MCK. DDRCK is equal to MCK.
25
24
–
H32MXDIV
17
16
–
–
9
8
MDIV
1
0
CSS
SAMA5D4 Series [DATASHEET]
Atmel-11238A-ATARM-SAMA5D4-Datasheet_30-Sep-14
317