SAMA5D41_14 Datasheet, PDF (85/1776 Pages) ATMEL Corporation – Atmel | SMART ARM-based Embedded MPU

14. L2 Cache Controller (L2CC)
14.1
Description
The L2 Cache Controller (L2CC) is based on the L2CC-PL310 ARM multi-way cache macrocell, version r3p2. The
addition of an on-chip secondary cache, also referred to as a Level 2 or L2 cache, is a method of improving the
system performance when significant memory traffic is generated by the processor.
14.2
Embedded Characteristics
 8-way set associative cache architecture
 Data banking is not supported
 No parity bit embedded
 Lockdown by master is not supported
 Lockdown by line is not supported
 TrustZone architecture for enhanced OS security
14.3 Product Dependencies
14.3.1 Power Management
The L2 Cache Controller is continuously clocked by the Processor Clock. The Power Management Controller has
no effect on the behavior of the L2 Cache Controller.
14.4
Functional Description
The addition of an on-chip secondary cache, also referred to as a Level 2 or L2 cache, is a recognized method of
improving the performance of ARM-based systems when significant memory traffic is generated by the processor.
By definition a secondary cache assumes the presence of a Level 1 or primary cache, closely coupled or internal
to the processor. Memory access is fastest to L1 cache, followed closely by L2 cache. Memory access is typically
significantly slower with L3 main memory.
The cache controller is a unified, physically addressed, physically tagged cache with up to 8 ways. User can lock
the replacement algorithm on a way basis, enabling the associativity to be reduced from 8-way down to 1-way
(directly mapped).
The cache controller does not have snooping hardware to maintain coherency between caches, so the user has to
maintain coherency by software.
14.4.1 Double Linefill Issuing
The L2CC cache line length is 32-byte. Therefore, by default, on each L2 cache miss,
L2CC issues 32-byte linefills, 4 x 64-bit read bursts, to the L3 memory system. L2CC can issue 64-byte linefills, 8
x 64-bit read bursts, on an L2 cache miss. When the L2CC is waiting for the data from L3, it performs a lookup on
the second cache line targeted by the 64-byte linefill. If it misses, data corresponding to the second cache line are
allocated to the L2 cache. If it hits, data corresponding to the second cache line are discarded.
SAMA5D4 Series [DATASHEET]
85
Atmel-11238A-ATARM-SAMA5D4-Datasheet_30-Sep-14