SAMA5D41_14 Datasheet, PDF (223/1776 Pages) ATMEL Corporation – Atmel | SMART ARM-based Embedded MPU

Figure 20-5. User Reset State
SLCK
MCK
NRST
proc_nreset
RSTTYP
periph_nreset
Any
Freq.
Resynch.
2 cycles
Any
Resync.
2 cycles
Processor Startup
XXX
0x4 = User Reset
20.4.3.4 Software Reset
The Reset Controller offers several commands used to assert the different reset signals. These commands are
performed by writing the Control Register (RSTC_CR) with the following bits at 1:
 PROCRST: Writing PROCRST at 1 resets the processor and the watchdog timer.
 PERRST: Writing PERRST at 1 resets all the embedded peripherals, including the memory system, and, in
particular, the Remap Command. The Peripheral Reset is generally used for debug purposes.
PERRST must always be used in conjunction with PROCRST (PERRST and PROCRST set both at 1
simultaneously.)
The software reset is entered if at least one of these bits is set by the software. All these commands can be
performed independently or simultaneously. The software reset lasts 2 Slow Clock cycles.
The internal reset signals are asserted as soon as the register write is performed. This is detected on the Master
Clock (MCK). They are released when the software reset is left, i.e., synchronously to SLCK.
If and only if the PROCRST bit is set, the reset controller reports the software status in the field RSTTYP of the
RSTC_SR. Other software resets are not reported in RSTTYP.
As soon as a software operation is detected, the bit SRCMP (Software Reset Command in Progress) is set in the
RSTC_SR. It is cleared as soon as the software reset is left. No other software reset can be performed while the
SRCMP bit is set, and writing any value in RSTC_CR has no effect.
SAMA5D4 Series [DATASHEET]
Atmel-11238A-ATARM-SAMA5D4-Datasheet_30-Sep-14
223